MTS Silicon Design Engineer

Apr 29, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SOC Physical Design Engineer

THE ROLE:

Physical design including block level place/cts/route, full chip floor planning, timing closure, physical verification etc.

 

THE PERSON:

  • Always be positive, dedicated and good team player
  • Good listening, writing, and speaking English
  • Good communication skills

 

KEY RESPONSIBILITIES:

  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
  • Focus on physical design of deep sub-micron GPU chips including block level, full chip floor planning, timing closure, place and route, physical verification etc.
  • The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. 
  • The individual is also expected to be accountable for project delivery.

 

PREFERRED EXPERIENCE:

  • Tape-out experience in deep submicron process
  • Knowledgeable in all aspects of ASIC design flow
  • Demonstrate strong leadership and work well with cross-functional teams
  • Hands on experience in physical design is a plus
  • Demonstrate strong leadership, work well with cross-functional teams
  • Familiar with Unix/Linux environment
  • Familiar with Back-End (physical design) EDA tools is a plus
  • Familiar with Front-End EDA tools is a plus
  • Good at scripts, like Python/perl/Tcl/shell

 

ACADEMIC CREDENTIALS:

  • MSEE / Microelectronic preferred
  • CET-6 preferred
  • MSEE with 5+ years or Bachelor with 8+ years of industrial experience in ASIC design 

 

LOCATION:

Shanghai

 

#LI-VC1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SOC Physical Design Engineer

THE ROLE:

Physical design including block level place/cts/route, full chip floor planning, timing closure, physical verification etc.

 

THE PERSON:

  • Always be positive, dedicated and good team player
  • Good listening, writing, and speaking English
  • Good communication skills

 

KEY RESPONSIBILITIES:

  • Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
  • Focus on physical design of deep sub-micron GPU chips including block level, full chip floor planning, timing closure, place and route, physical verification etc.
  • The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. 
  • The individual is also expected to be accountable for project delivery.

 

PREFERRED EXPERIENCE:

  • Tape-out experience in deep submicron process
  • Knowledgeable in all aspects of ASIC design flow
  • Demonstrate strong leadership and work well with cross-functional teams
  • Hands on experience in physical design is a plus
  • Demonstrate strong leadership, work well with cross-functional teams
  • Familiar with Unix/Linux environment
  • Familiar with Back-End (physical design) EDA tools is a plus
  • Familiar with Front-End EDA tools is a plus
  • Good at scripts, like Python/perl/Tcl/shell

 

ACADEMIC CREDENTIALS:

  • MSEE / Microelectronic preferred
  • CET-6 preferred
  • MSEE with 5+ years or Bachelor with 8+ years of industrial experience in ASIC design 

 

LOCATION:

Shanghai

 

#LI-VC1

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