MTS Silicon Design Engineer

May 08, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




MTS SILICON DESIGN ENGINEER 

THE ROLE: 

  • Work with global hard IP team/package team/FTO team/physical design team for large scale ASIC chip physical implementation and verification.  

  • Focus on SOC level physical verification signoff, including drc/lvs/antenna/lupesd/perc etc. on leading process.  

  • Include RDL routing implementation of deep sub-micron chips including signal/power/ground RDL.  

THE PERSON: 

  • Strong self-learning and self-driven abilities, strong curiosity on new technologies.  

  • Good communication skills, proactive and teamwork.  

  • Good spoken and written English. 

KEY RESPONSIBILITIES: 

  • Provide guidance and solutions to FCFP/Flow team and other stake holders on the PhyV requirement during construction.  

  • Run SOC level PhyV checks(including DRC/LVS/PERC/LUPESD etc.) , review results, provide solutions for issues, make sure all checks are clean before tapeout.   

  • RDL routing implementation for special analog Ips to meet IP requirement and ESD requirements.    

 

PREFERRED EXPERIENCE: 

  • Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a must.  

  • Familiar with general IC design flow, familiar with digital physical design flow and EDA tool (Synopsys ICV and Mentor Calibre) is preferred.  

  • Knowledge on SVRF deck coding is preferred.  

  • Experience on SOC level physical verification signoff(drc/lvs/antenna/lupesd/perc etc.) on advanced technology is preferred. 

  • Knowledge of SOC ESD protection and ESD perc check is preferred. 

  • Background on foundary PDK or analog layout design can also be candidates.  

 

ACADEMIC CREDENTIALS: 

  • Major in Electrical/Electronics/Micro Electronics/Material or other technology Engineerings   

  • Bachelor's Degree with 6+ years of related experience, or Master’s degree with 4+ years of related experience, or PhD degree with 2+ years of related experience.  

 

LOCATION: 

Shanghai 

 

#LI-VC1 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

THE ROLE: 

  • Work with global hard IP team/package team/FTO team/physical design team for large scale ASIC chip physical implementation and verification.  

  • Focus on SOC level physical verification signoff, including drc/lvs/antenna/lupesd/perc etc. on leading process.  

  • Include RDL routing implementation of deep sub-micron chips including signal/power/ground RDL.  

THE PERSON: 

  • Strong self-learning and self-driven abilities, strong curiosity on new technologies.  

  • Good communication skills, proactive and teamwork.  

  • Good spoken and written English. 

KEY RESPONSIBILITIES: 

  • Provide guidance and solutions to FCFP/Flow team and other stake holders on the PhyV requirement during construction.  

  • Run SOC level PhyV checks(including DRC/LVS/PERC/LUPESD etc.) , review results, provide solutions for issues, make sure all checks are clean before tapeout.   

  • RDL routing implementation for special analog Ips to meet IP requirement and ESD requirements.    

 

PREFERRED EXPERIENCE: 

  • Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a must.  

  • Familiar with general IC design flow, familiar with digital physical design flow and EDA tool (Synopsys ICV and Mentor Calibre) is preferred.  

  • Knowledge on SVRF deck coding is preferred.  

  • Experience on SOC level physical verification signoff(drc/lvs/antenna/lupesd/perc etc.) on advanced technology is preferred. 

  • Knowledge of SOC ESD protection and ESD perc check is preferred. 

  • Background on foundary PDK or analog layout design can also be candidates.  

 

ACADEMIC CREDENTIALS: 

  • Major in Electrical/Electronics/Micro Electronics/Material or other technology Engineerings   

  • Bachelor's Degree with 6+ years of related experience, or Master’s degree with 4+ years of related experience, or PhD degree with 2+ years of related experience.  

 

LOCATION: 

Shanghai 

 

#LI-VC1 

COMPANY JOBS
1501 available jobs
WEBSITE