MTS Silicon Design Engineer

Jun 30, 2022
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

MTS Silicon Design Engineer (DFT)

 

THE ROLE:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products. It is also responsible for DFx design methodology and CAD automation tools development to support the global DFX engineering teams across AMD.

 

THE PERSON:

As a DFx Silicon Design Engineer, you will be working with a team of design engineers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives.  This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

 

KEY RESPONSIBILITIES:

  • Develop RTL for ASIC design-for-test (DFT) features as per architectural or design flow automation specifications
  • Perform RTL design integration, insertion, synthesis, equivalency checking, timing analysis and closure including defining constraints
  • Develop scan compression insertion and stitching flow automation
  • Perform scan ATPG/DRC verification, pattern generation and simulation
  • Deliver production quality ATPG patterns to product engineering team, and provide pattern bring-up support on first silicon
  • Debugging and verifying block-/chip-level DFT/DFX features(plus)
  • Porting or creating the DFT/DFX verification environment(plus)
  • Block/chip test plan creation and development(plus)
  • Stimulus writing and debug, and regression clean-up(plus)

 

PREFERRED EXPERIENCE:

  • Good understanding of computing/graphics design architecture
  • Familiar with ASIC design, fabrication, assembly and ATE test
  • Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST is a plus
  • Good working knowledge of UNIX/Linux and scripting languages (e.g., TCL, c-shell, Perl)
  • Familiar with Verilog design language, Verilog simulator and waveform debugging tools
  • Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus
  • Strong problem-solving skills
  • Team player with strong communication skills

 

ACADEMIC CREDENTIALS:

B.Sc. in Electrical or Computer Engineering (or equivalent)

 

LOCATION:

ShangHai, China



Requisition Number: 171284 
Country/Region/Location: China State/Province: Shanghai City: Shanghai 
Job Function: 
Design  

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