MTS Silicon Design Engineer

Jan 23, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

  • As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
  • The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
  • Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.
  • The IP team will have flexible work assignment, respect to indificual interest and the team target to achieve win-win, encourage and help individuals to discuss with global senior architectures and engineers for variants of topics and work together to resolve problems, aimed to improve both the team and individuals’ IP design capability and competivity.

 

THE PERSON:

  • Strong experience in ASIC/SoC design
  • Strong hands-on verilog development experience, familiar with scripting languages like Perl
  • Good experience on complicate hub,control IP design
  • Strong problem solving, independent thinking, teamwork and communication skills

 

KEY RESPONSIBILITIES:

  • Own part of IP feature design with cooperation with other designers

 

PREFERRED EXPERIENCE:

  • Knowledge on AXI, PCIE is a big plus.
  • Better to have knowledge on x86 system view, embedded hw design with hw/sw/fw co-operation experience.

 

 

ACADEMIC CREDENTIALS:

  • Preferred MS degree.

#LI-JG2

#LI-Hybrid 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

  • As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
  • The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
  • Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.
  • The IP team will have flexible work assignment, respect to indificual interest and the team target to achieve win-win, encourage and help individuals to discuss with global senior architectures and engineers for variants of topics and work together to resolve problems, aimed to improve both the team and individuals’ IP design capability and competivity.

 

THE PERSON:

  • Strong experience in ASIC/SoC design
  • Strong hands-on verilog development experience, familiar with scripting languages like Perl
  • Good experience on complicate hub,control IP design
  • Strong problem solving, independent thinking, teamwork and communication skills

 

KEY RESPONSIBILITIES:

  • Own part of IP feature design with cooperation with other designers

 

PREFERRED EXPERIENCE:

  • Knowledge on AXI, PCIE is a big plus.
  • Better to have knowledge on x86 system view, embedded hw design with hw/sw/fw co-operation experience.

 

 

ACADEMIC CREDENTIALS:

  • Preferred MS degree.

#LI-JG2

#LI-Hybrid 

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