MTS Silicon Design Engineer

Feb 28, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

As a Design-for-Debug (DFD) engineer, you should have DFD end to end execution experience from DFD spec definition to post silicon bring up. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion. You will directly work on cutting edge DFD technology and address the challenge of AMD leading SOC.

 

THE PERSON:

  • Hands on working experience on ASIC DFD design and verification
  • Familiar with modern ASIC design flow
  • Should have strong problem-solving skills

KEY RESPONSIBILITIES:

Qualified candidate will perform some or all functions below:

  • Working with a multi-discipline and international team of engineers on design-for-debug (DFD) architecture, design and methodology initiatives. 
  • Performing DFD RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints.
  • Writing and maintain DFD documentation, presentation material and specifications.
  • Support the integration/verification of DFD IP into other IP and at the SoC-level.
  • Support post silicon bring up and debug.

 

PREFERRED EXPERIENCE:

  • Good English hearing, speaking, reading, and writing capabilities
  • Good communication skills
  • Experience in solving logic design or timing issues with integration, synthesis, and PD teams
  • Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging simulations

 

ACADEMIC CREDENTIALS:

  • BS or MS in EE & CS.  Preferred 3+ years experiences

LOCATION:

  • Shanghai or Beijing

#LI-VC1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

As a Design-for-Debug (DFD) engineer, you should have DFD end to end execution experience from DFD spec definition to post silicon bring up. You will meet regularly with other functional team members such as Architects, Verification Engineers, Physical Designers, CAD Engineers, SoC Design Engineers, Product Engineers and Program Management to ensure successful and timely project completion. You will directly work on cutting edge DFD technology and address the challenge of AMD leading SOC.

 

THE PERSON:

  • Hands on working experience on ASIC DFD design and verification
  • Familiar with modern ASIC design flow
  • Should have strong problem-solving skills

KEY RESPONSIBILITIES:

Qualified candidate will perform some or all functions below:

  • Working with a multi-discipline and international team of engineers on design-for-debug (DFD) architecture, design and methodology initiatives. 
  • Performing DFD RTL integration, synthesis, equivalency checking, timing analysis and closure including defining design constraints.
  • Writing and maintain DFD documentation, presentation material and specifications.
  • Support the integration/verification of DFD IP into other IP and at the SoC-level.
  • Support post silicon bring up and debug.

 

PREFERRED EXPERIENCE:

  • Good English hearing, speaking, reading, and writing capabilities
  • Good communication skills
  • Experience in solving logic design or timing issues with integration, synthesis, and PD teams
  • Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging simulations

 

ACADEMIC CREDENTIALS:

  • BS or MS in EE & CS.  Preferred 3+ years experiences

LOCATION:

  • Shanghai or Beijing

#LI-VC1

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