MTS Silicon Design Engineer

Mar 13, 2024
Shanghai, China
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE: 

Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of System reset and boot, network-on-chip, data compression, advanced power management, clocking, etc. The SRDC CF team is a critical part of global CF team.  

 

THE PERSON: 

Candidate will work as design engineer in CF team on development of industry leading chiplet fabric.

 

KEY RESPONSIBILITIES: 

  • Block level and subsystem level micro-architecture spec, RTL design, synthesize and timing closure
  • Collaborate with verification team to achieve good coverage
  • Deliver CF IP to SoCs, meeting power, area, timing, schedule bounding box, and other metrics

 

PREFERRED EXPERIENCE: 

  • Strong skills on Verilog HDL or System Verilog
  • Strong knowledge on AMBA(AXI/AHB/APB) bus
  • Familiar with Front-End design and implementation flow
  • Knowledge on synthesis, STA, CDC
  • Network-on-chip experience is a plus
  • Low power design experience is a plus
  • Good skills on Perl/Python script
  • Strong analytical and problem-solving skills
  • Excellent communication skills and experience collaborating with other engineers
  • Fluent English communication skills(listening, speaking and writing)  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

LOCATION:

Shanghai

 

#LI-VC1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

Control Fabric (CF) IP is the backbone of AMD SOCs. We design and deliver cutting-edge technologies of System reset and boot, network-on-chip, data compression, advanced power management, clocking, etc. The SRDC CF team is a critical part of global CF team.  

 

THE PERSON: 

Candidate will work as design engineer in CF team on development of industry leading chiplet fabric.

 

KEY RESPONSIBILITIES: 

  • Block level and subsystem level micro-architecture spec, RTL design, synthesize and timing closure
  • Collaborate with verification team to achieve good coverage
  • Deliver CF IP to SoCs, meeting power, area, timing, schedule bounding box, and other metrics

 

PREFERRED EXPERIENCE: 

  • Strong skills on Verilog HDL or System Verilog
  • Strong knowledge on AMBA(AXI/AHB/APB) bus
  • Familiar with Front-End design and implementation flow
  • Knowledge on synthesis, STA, CDC
  • Network-on-chip experience is a plus
  • Low power design experience is a plus
  • Good skills on Perl/Python script
  • Strong analytical and problem-solving skills
  • Excellent communication skills and experience collaborating with other engineers
  • Fluent English communication skills(listening, speaking and writing)  

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

LOCATION:

Shanghai

 

#LI-VC1

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