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MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The focus of this role is to perform transistor level static timing analysis (STA) on analog and mixed signals blocks, validating the timing performance and generating accurate timing models to enable next level analysis.

THE PERSON:  

You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.  You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  You are self-driven and highly motivated to work on new and challenging tasks.  You are pragmatic and has good problem-solving skills.  Organized and documents well. 

KEY RESPONSIBILITIES:  

• Collaborate with various stakeholders to understand the blocks features and requirements for timing closure and timing model generation.  
• Work with design teams to Build timing constraints and qualify them. 
• Work closely with top level STA team and physical design team to resolve any timing related issues. 
• Review timing reports with design teams to ensure no timing violations on all timing paths. 
• Propose and develop scripts to perform QA checks to ensure all timing models released are of the highest quality.  

PREFERRED EXPERIENCE:  

• Experienced in working on advanced process nodes (finfet).
• Experienced with modern digital, analog, mixed signal IC design flows.  Analog design, layout verification, parasitic extraction and timing concepts etc.
• Proficient in STA Tools (NanoTime).  Good working knowledge on clock definitions, timing constraints, topology constraints, exceptions with some related experience. 
• Understanding of margining methodologies to address process variation, correlation to spice, silicon.
• Identify, propose and automate QA checks to ensure quality of runs and deliverables. 
• Knowledge of timing corners/modes and process variations.
• In-depth understanding of Liberty format (NLDM, CCS, ECSM).
• Experience of library characterization tools such as SiliconSmart is a plus.
• Scripting skills in tcl, perl, or python.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in Electrical/Electronics Engineering.

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER  

THE ROLE: 

The focus of this role is to perform transistor level static timing analysis (STA) on analog and mixed signals blocks, validating the timing performance and generating accurate timing models to enable next level analysis.

THE PERSON:  

You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones.  You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.  You are self-driven and highly motivated to work on new and challenging tasks.  You are pragmatic and has good problem-solving skills.  Organized and documents well. 

KEY RESPONSIBILITIES:  

• Collaborate with various stakeholders to understand the blocks features and requirements for timing closure and timing model generation.  
• Work with design teams to Build timing constraints and qualify them. 
• Work closely with top level STA team and physical design team to resolve any timing related issues. 
• Review timing reports with design teams to ensure no timing violations on all timing paths. 
• Propose and develop scripts to perform QA checks to ensure all timing models released are of the highest quality.  

PREFERRED EXPERIENCE:  

• Experienced in working on advanced process nodes (finfet).
• Experienced with modern digital, analog, mixed signal IC design flows.  Analog design, layout verification, parasitic extraction and timing concepts etc.
• Proficient in STA Tools (NanoTime).  Good working knowledge on clock definitions, timing constraints, topology constraints, exceptions with some related experience. 
• Understanding of margining methodologies to address process variation, correlation to spice, silicon.
• Identify, propose and automate QA checks to ensure quality of runs and deliverables. 
• Knowledge of timing corners/modes and process variations.
• In-depth understanding of Liberty format (NLDM, CCS, ECSM).
• Experience of library characterization tools such as SiliconSmart is a plus.
• Scripting skills in tcl, perl, or python.

ACADEMIC CREDENTIALS:  

• Bachelors or Masters degree in Electrical/Electronics Engineering.

#LI-LL1

#LI-HYBRID