MTS Silicon Design Engineer ( Soc /IP Verification Lead)

Jan 25, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

This is an exciting opportunity in IP Verification, to work on IPs based on PCIe, CXL, DMA and NVMe technologies in AECG business group in AMD. The candidate will have the opportunity to work and develop on state-of-art UVM based verification environment on highly-configurable IPs designed for adaptive computing products targeted for datacenter performance and acceleration needs.

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Verifying RTL implementation for complex digital blocks to ensure high quality
  • Developing verification strategies for new features, plan volume validation and coverage strategies
  • Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
  • Working with designers to do coverage analysis and take necessary actions to meet coverage goals
  • Integrate VIPs as needed
  • Closely work with design teams to drive feature enablement
  • Mentor Junior Engineers on the team.

PREFERRED EXPERIENCE: 

  • Working experience on PCIe, DMA, CXL and/or NVMe  protocols required
  • Knowledge of bus protocols like AXI/AHB desired
  • Grounds-up development experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
  • Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
  • Highly motivated, Self-starter individual with ability to work in a fast-paced team environment

ACADEMIC CREDENTIALS: 

  • BS in EE/CE &  10+ years of experience, or an MS in EE/CE & 7+ years of experience in pre-silicon verification

 

#LI-SR4




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

This is an exciting opportunity in IP Verification, to work on IPs based on PCIe, CXL, DMA and NVMe technologies in AECG business group in AMD. The candidate will have the opportunity to work and develop on state-of-art UVM based verification environment on highly-configurable IPs designed for adaptive computing products targeted for datacenter performance and acceleration needs.

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

KEY RESPONSIBILITIES: 

  • Verifying RTL implementation for complex digital blocks to ensure high quality
  • Developing verification strategies for new features, plan volume validation and coverage strategies
  • Writing testplan, developing testbenches, coding test/sequences and checker to support IP level verification in constrained-random and/or directed verification environments using System Verilog & UVM
  • Working with designers to do coverage analysis and take necessary actions to meet coverage goals
  • Integrate VIPs as needed
  • Closely work with design teams to drive feature enablement
  • Mentor Junior Engineers on the team.

PREFERRED EXPERIENCE: 

  • Working experience on PCIe, DMA, CXL and/or NVMe  protocols required
  • Knowledge of bus protocols like AXI/AHB desired
  • Grounds-up development experience with implementation of UVM/OVM and/or Verilog, System Verilog test benches and/or BFMs is required
  • Strong understanding of simulation tools and knowledge of scripting languages like Perl, tcl or cshell
  • Highly motivated, Self-starter individual with ability to work in a fast-paced team environment

ACADEMIC CREDENTIALS: 

  • BS in EE/CE &  10+ years of experience, or an MS in EE/CE & 7+ years of experience in pre-silicon verification

 

#LI-SR4

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