MTS Silicon Design Engineer(204)

Sep 09, 2022
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 


At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

 

Masters or Bachelors in EE/ECE, 8-12 years of relevant experience in VLSI domain.

 

As an MTS level fullchip STA engineer, you would be leading a team of individuals towards leading edge SOC subsystem timing closure.

Good understanding of complete ASIC PD/timing closure flow, with hands on experience leading teams driving timing closure. Should have experience using industry standard STA tools like Primetime, PT based tcl scripting. Should have experience with block and full-chip constraints development and providing guidance to RTL and PD teams to help the timing spec. Should understand the complete physical design aspects/stages related to timing closure. Any hands-on with PNR would be helpful. Strong understanding of Digital, CMOS, Crosstalk, OCV, IR-drop, EM, Process variations and other STA concepts. Should be able to operate independently and own timing closure of individual blocks/sub-systems, leading and mentoring a team of junior designers. Good verbal and written communication skills is a must. Should be a very good team player and be willing to contribute to cross functional and cross geographical team endeavors in terms of methodology and design process improvements.

 

#LN-SH4



Requisition Number: 181341 
Country/Region/Location: India State/Province: Telangana City: Hyderabad 
Job Function: 
Design  

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