MTS Silicon RTL Design Engineer

Feb 15, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

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Silicon RTL Design Engineer

The role:

An RTL Design Engineering role in our Security IP (SECIP) team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our design engineers will work on block level RTL design and/or subsystem level integration for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

The person:

A talented hardware RTL design engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystems design and associated verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

  • Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
  • Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
  • Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
  • Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
  • Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams
  • Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

Preferred experience:

  • BSc with a minimum of 5 years of relevant experience; or MSc with a minimum of 3 years; or PhD in a directly related research area and a minimum of 1 equivalent year
  • Proven understanding of CPU and MP subsystem architecture, datapath accelerator RTL microarchitecture, as well as FPGA based simulation or emulation methodology
  • Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile)
  • Excellent knowledge about state-of-art RTL design and verification methodology and best practices, and C-DPI test design
  • Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
  • Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

Academic credentials:

  • Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
  • Master's Degree preferred

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Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Silicon RTL Design Engineer

The role:

An RTL Design Engineering role in our Security IP (SECIP) team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our design engineers will work on block level RTL design and/or subsystem level integration for a variety of embedded MP subsystems. Your expertise will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.

The person:

A talented hardware RTL design engineer with strong records of technical ownership and execution to drive block level IP and/or MP subsystems design and associated verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

  • Develop and maintain block level RTL IP and MP subsystems’ feature spec, micro-architecture, synthesizable RTL design methodology and infrastructure
  • Develop and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests, and achieve design feature closure (feature spec vs. coverage metrics)
  • Triage regressions, debug specific simulations, analyze coverage, and work/resolve technical issues with design, verification, and other teams to achieve design feature and design rule closures (linting, timing, DFT, DFP and other rules)
  • Participate in verification testbench and test plan specification, influence testbench architecture development (design for verification aspect), review and improve feature and coverage test plans
  • Debug and resolve integration issues with SoC Integration, SoC DV and post-silicon validation teams
  • Provide technical leadership in IP functionality and design methodology development as well as critical problem resolution if as advanced level team members

Preferred experience:

  • BSc with a minimum of 5 years of relevant experience; or MSc with a minimum of 3 years; or PhD in a directly related research area and a minimum of 1 equivalent year
  • Proven understanding of CPU and MP subsystem architecture, datapath accelerator RTL microarchitecture, as well as FPGA based simulation or emulation methodology
  • Proficient in Verilog, System Verilog (an extra asset), and scripting (using Tcl, Ruby, Perl, Python and Makefile)
  • Excellent knowledge about state-of-art RTL design and verification methodology and best practices, and C-DPI test design
  • Excellent understanding of standard bus/interface protocols (i.e. AXI, AHB, AMBA)
  • Proven experience with ASIC design tools: synthesis, linting, simulation, debugging, power aware simulation, etc.
  • Relevant design domain specific knowledge and technical leadership capability required for advanced level candidates

Academic credentials:

  • Bachelor's Degree or Master's Degree in Electrical Engineering, Computer Engineering, or Computer Science, or possibly a related field
  • Master's Degree preferred

#LI-SH1

#LI-HYBRID

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