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MTS SILICON DESIGN ENGINEER
THE ROLE:
The position will involve working with a very experienced circuit design team of SRAM FPGA macros and is responsible for delivering the macro design to meet challenging goals for frequency, power and other design requirements for AMD next generation FPGAs in a fast-paced environment on cutting edge technology.
THE PERSON:
Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.
KEY RESPONSIBILITIES:
• Good Understanding of SRAM, ROM and digital circuit design
• Implementing Design Schematic
• Circuit design and debug
• Silicon issue debug
• Knowledge of DFT
• Statistical analysis of design
• Logical equivalence check of design
• Handling Internal timings, Power, Leakage, Crosstalk Analysis(noise), Electromigration, IR drop
• Handling different design tools – Cadence Virtuoso, Formality, ESP-CV, NanoTime, Hspice, StarRC, Mentor Graphics Calibre
PREFERRED EXPERIENCE:
• 10+ years of professional experience in SRAM/ROM design, preferably with high performance memory circuit designs.
• Experience in high-speed SRAM design
• Experience in checks for logic equivalence
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Excellent layout understanding.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-SR4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
THE ROLE:
The position will involve working with a very experienced circuit design team of SRAM FPGA macros and is responsible for delivering the macro design to meet challenging goals for frequency, power and other design requirements for AMD next generation FPGAs in a fast-paced environment on cutting edge technology.
THE PERSON:
Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player.
KEY RESPONSIBILITIES:
• Good Understanding of SRAM, ROM and digital circuit design
• Implementing Design Schematic
• Circuit design and debug
• Silicon issue debug
• Knowledge of DFT
• Statistical analysis of design
• Logical equivalence check of design
• Handling Internal timings, Power, Leakage, Crosstalk Analysis(noise), Electromigration, IR drop
• Handling different design tools – Cadence Virtuoso, Formality, ESP-CV, NanoTime, Hspice, StarRC, Mentor Graphics Calibre
PREFERRED EXPERIENCE:
• 10+ years of professional experience in SRAM/ROM design, preferably with high performance memory circuit designs.
• Experience in high-speed SRAM design
• Experience in checks for logic equivalence
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Excellent layout understanding.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-SR4