WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:
We are looking for an adaptive, self-motivated senior design micro-architect & leader to join our growing team.
As a member of the PCIe/CXL Design team, you will help bring to life cutting-edge designs, you will work closely with the architecture, Physical Design, and Design verification teams, and product engineers to achieve first pass silicon success.

THE PERSON:

Experienced team leader/Technical Leader who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. Have a passion for modern, complex microarchitecture, and digital design.
Strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Someone who wants to mentor, manage and lead a team through successful project completion. 

KEY RESPONSIBLITIES:

• Participate in the definition of microarchitecture of next-generation high-performance PCIe/CXL connectivity solutions.
• Lead a team of hardware engineers, responsible for Milestone and scheduled delivery to various teams.
• Execute on RTL design and coding for various sections of the SOC.
• Contribute to silicon debug and product support as needed.

PREFERRED EXPERIENCE:

• Strong experience with PCIe, CXL
• Relevant and proven experience of RTL design, Verilog and System Verilog
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Validated experience with synthesis, static timing, DFT, ECO is a plus
• Exposure to physical design and verification methods
• Experience with scripting languages including Perl, Python, Unix shells and Makefiles
• Strong communication, collaboration and presentation skills

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:  San Jose, CA 

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:
We are looking for an adaptive, self-motivated senior design micro-architect & leader to join our growing team.
As a member of the PCIe/CXL Design team, you will help bring to life cutting-edge designs, you will work closely with the architecture, Physical Design, and Design verification teams, and product engineers to achieve first pass silicon success.

THE PERSON:

Experienced team leader/Technical Leader who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. Have a passion for modern, complex microarchitecture, and digital design.
Strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Someone who wants to mentor, manage and lead a team through successful project completion. 

KEY RESPONSIBLITIES:

• Participate in the definition of microarchitecture of next-generation high-performance PCIe/CXL connectivity solutions.
• Lead a team of hardware engineers, responsible for Milestone and scheduled delivery to various teams.
• Execute on RTL design and coding for various sections of the SOC.
• Contribute to silicon debug and product support as needed.

PREFERRED EXPERIENCE:

• Strong experience with PCIe, CXL
• Relevant and proven experience of RTL design, Verilog and System Verilog
• Deep knowledge of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Validated experience with synthesis, static timing, DFT, ECO is a plus
• Exposure to physical design and verification methods
• Experience with scripting languages including Perl, Python, Unix shells and Makefiles
• Strong communication, collaboration and presentation skills

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION:  San Jose, CA 

#LI-DW1

#LI-HYBRID