WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SENIOR SILICON DESIGN ENGINEER 

KEY RESPONSIBILITIES:  

• This position is for a physical design engineer in AMD’s Radeon Technology Group working on next generation graphics processors. Responsibilities include Block and/or Chip Level Floor planning, FC level Clock Routing, Bump Routing, RDL layer Routing, Physical Verification, Signoff checks. Understanding of Placement, Optimization, Clock tree synthesis, Routing, Parasitic Extraction, IR drop analysis, Physical Verification and Sign Off flows. Flow automation using perl/tcl programming.

REQUIREMENTS:

• Experience in ASIC Physical Design from RTL to GDSII.
• Tasks include full chip level physical verification, clock routing, Power/IO Bump planning, RDL routing.
• Experienced in Layout design, Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
• Strong communication and presentation skill, experience in working with global team
• Hands on experience in taping out 3nm, 5nm, 7nm, SOC design.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior engineers, and be an effective team player

#LI-ST1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SENIOR SILICON DESIGN ENGINEER 

KEY RESPONSIBILITIES:  

• This position is for a physical design engineer in AMD’s Radeon Technology Group working on next generation graphics processors. Responsibilities include Block and/or Chip Level Floor planning, FC level Clock Routing, Bump Routing, RDL layer Routing, Physical Verification, Signoff checks. Understanding of Placement, Optimization, Clock tree synthesis, Routing, Parasitic Extraction, IR drop analysis, Physical Verification and Sign Off flows. Flow automation using perl/tcl programming.

REQUIREMENTS:

• Experience in ASIC Physical Design from RTL to GDSII.
• Tasks include full chip level physical verification, clock routing, Power/IO Bump planning, RDL routing.
• Experienced in Layout design, Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
• Strong communication and presentation skill, experience in working with global team
• Hands on experience in taping out 3nm, 5nm, 7nm, SOC design.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior engineers, and be an effective team player

#LI-ST1