Performance Silicon Design Engineer

Feb 01, 2024
Iaşi, Romania
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SILICON DESIGN PERFORMANCE ENGINEER 
 

The Role

As a Silicon Design Performance Engineer, you will work closely with the architecture, design, and modeling teams working on high-performance systems-on-chip (SOC) interconnect designs, responsible for register transfer level (RTL) performance analysis and microbenchmarking for the Fabric Interconnect IP.

  

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

Key Responsibilities

  • Execute on microbenchmarking plans at the IP level, and support performance debug at the SOC level
  • Conduct theoretical analysis of the on-chip network bandwidth and latency, setting up benchmarks to run in RTL simulations, maintaining or enhancing regression scripts to automate them, debugging cases where benchmarks fail their performance metrics, identifying design bottle necks and proposing solutions
  • Work on debug tools, or fixes for any issues seen in the performance benchmarking environment to deliver the highest performing Interconnect IP under given design parameters for planned production 

 

Preferred Experience

  • Project level experience with design concepts and RTL implementation for same 
  • Experience or familiarity with functional verification tools by VCS, Cadence, Mentor Graphics 
  • Experience or familiarity with the following: C++, Verilog, SystemVerilog
  • Good understanding of computer organization/architecture 

 

Academic Credentials

  • Bachelor’s or Master’s degree in computer engineering/Electrical Engineering

 

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Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN PERFORMANCE ENGINEER 
 

The Role

As a Silicon Design Performance Engineer, you will work closely with the architecture, design, and modeling teams working on high-performance systems-on-chip (SOC) interconnect designs, responsible for register transfer level (RTL) performance analysis and microbenchmarking for the Fabric Interconnect IP.

  

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

Key Responsibilities

  • Execute on microbenchmarking plans at the IP level, and support performance debug at the SOC level
  • Conduct theoretical analysis of the on-chip network bandwidth and latency, setting up benchmarks to run in RTL simulations, maintaining or enhancing regression scripts to automate them, debugging cases where benchmarks fail their performance metrics, identifying design bottle necks and proposing solutions
  • Work on debug tools, or fixes for any issues seen in the performance benchmarking environment to deliver the highest performing Interconnect IP under given design parameters for planned production 

 

Preferred Experience

  • Project level experience with design concepts and RTL implementation for same 
  • Experience or familiarity with functional verification tools by VCS, Cadence, Mentor Graphics 
  • Experience or familiarity with the following: C++, Verilog, SystemVerilog
  • Good understanding of computer organization/architecture 

 

Academic Credentials

  • Bachelor’s or Master’s degree in computer engineering/Electrical Engineering

 

#LI-PD1

#LI-HYBRID

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