Physical Design Clocking Engineer

May 07, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

The focus of this role is to plan and implement global clock trees which is very critical in AMD’s advanced processors, meeting requirements of timing, power and area.

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

  • Collaborate with timing, floorplan, and P&R teams to create plans for global clock.
  • Build global clock trees for easier timing closure with reasonable power and area.
  • Resolve placement and routing DRC violations of global clock trees.
  • Verify global clock trees quality with SPICE simulations and PrimeTime STA analysis.
  • Perform ECO changes on clock to fix electrical violations and to help timing closure.

PREFERRED EXPERIENCE:  

  • Knowledge in CMOS digital circuits.
  • Familiar with Physical Design flow.
  • Experienced in using P&R, timing analysis, and physical verification CAD tools.
  • Scripting language experience: Tcl, shell, Python, Perl preferred.
  • Experience in analog design or computer algorithms is a plus.

  

ACADEMIC CREDENTIALS:  

  • Bachelor’s or Master’s degree in Computer Engineering/Electrical Engineering.

 

#LI-IA1

#LI-Hybrid

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

The focus of this role is to plan and implement global clock trees which is very critical in AMD’s advanced processors, meeting requirements of timing, power and area.

  

THE PERSON:  

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

  

KEY RESPONSIBILITIES:  

  • Collaborate with timing, floorplan, and P&R teams to create plans for global clock.
  • Build global clock trees for easier timing closure with reasonable power and area.
  • Resolve placement and routing DRC violations of global clock trees.
  • Verify global clock trees quality with SPICE simulations and PrimeTime STA analysis.
  • Perform ECO changes on clock to fix electrical violations and to help timing closure.

PREFERRED EXPERIENCE:  

  • Knowledge in CMOS digital circuits.
  • Familiar with Physical Design flow.
  • Experienced in using P&R, timing analysis, and physical verification CAD tools.
  • Scripting language experience: Tcl, shell, Python, Perl preferred.
  • Experience in analog design or computer algorithms is a plus.

  

ACADEMIC CREDENTIALS:  

  • Bachelor’s or Master’s degree in Computer Engineering/Electrical Engineering.

 

#LI-IA1

#LI-Hybrid

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