WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

As a member of the Graphics Technologies and Engineering (G&E) Methodology and Technology team,

you will develop and improve design flows bringing to life cutting-edge designs in latest technologies. You will work closely with the Block level Physical Design, Full Chip Floorplan / Netlist, Full Chip Static Timing Analysis, CAD, Methodology and Technology Teams to achieve first pass silicon success.

 
THE PERSON:

Excellent analytical, project management, communication, detail oriented and problem solving skills.

Desire to innovate and find solutions in a fast-paced engineering environment.

Will work very closely with Fellows, Principal Engineers, Architects, Technology/CAD teams and collaborate with cross functional worldwide teams

KEY RESPONSIBILITIES:

• Tasks to include  Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off.
• Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff)
• Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
• Drive and hands-on flow development and scripting
• Technical and schedule discussion with multi-site engineers and managers 

REQUIREMENTS:

• Excellent analytical and problem solving skills along with attention to details
• Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations.
• Experience in Full Chip pipelining and buffering, HFN buffering and feed through planning will be plus.
• Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
• Hands on experience in taping out  7nm, 10nm, and 28nm SOC
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics 8. Strong communication, Time Management, and Presentation Skills
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Vancouver, BC

#LI-PA1 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

As a member of the Graphics Technologies and Engineering (G&E) Methodology and Technology team,

you will develop and improve design flows bringing to life cutting-edge designs in latest technologies. You will work closely with the Block level Physical Design, Full Chip Floorplan / Netlist, Full Chip Static Timing Analysis, CAD, Methodology and Technology Teams to achieve first pass silicon success.

 
THE PERSON:

Excellent analytical, project management, communication, detail oriented and problem solving skills.

Desire to innovate and find solutions in a fast-paced engineering environment.

Will work very closely with Fellows, Principal Engineers, Architects, Technology/CAD teams and collaborate with cross functional worldwide teams

KEY RESPONSIBILITIES:

• Tasks to include  Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off.
• Full chip and block level timing closure for various stages of the entire design process (RTL, Synthesis, Place and Route and STA Signoff)
• Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction.
• Drive and hands-on flow development and scripting
• Technical and schedule discussion with multi-site engineers and managers 

REQUIREMENTS:

• Excellent analytical and problem solving skills along with attention to details
• Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations.
• Experience in Full Chip pipelining and buffering, HFN buffering and feed through planning will be plus.
• Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
• Hands on experience in taping out  7nm, 10nm, and 28nm SOC
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics 8. Strong communication, Time Management, and Presentation Skills
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

LOCATION:

Vancouver, BC

#LI-PA1