Physical Design Engineer

Feb 28, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

AMD is looking for an experienced SOC Physical Design Lead and deliver the next generation of cutting-edge graphics designs. Role includes executing cutting edge Logical and physical implementation actvities 

 

 As part of the RTG SOC team, candidate will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

 

 

THE PERSON: 

  • Strong self-driving ability
  • Strong problem-solving skills with high drive for improvements
  • Should have excellent communication skills (both written and oral)
  • Team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

 

KEY RESPONSIBILITIES: 

  • Responsible for Synthesis, Physical Design, timing and Physical closure
  • Enabling new processes, methodologies and AI driven convervence on PPA
  • Manage a large team of internal and external resources
  • Responsible for ensuring the completion of the SOC chip on schedule with high QOR
  • Physical implementation of block level and subsystem level Next-Gen High Performance Graphics Cores
  • Contribute to Synthesis, Power Reduction, Timing Convergence & Floorplan efforts of block and subsystem

 

PREFERRED EXPERIENCE: 

  • Proven track record on successful Physical implementation execution of complex blocks/SOCs
  • Have an in depth understanding and experience for all  Physical Design activities for a large, leading technology SOC ASIC chip
  • Have strong management, technical problem solving, communication and presentation skills
  • Great team player able to effectively interact and collaborate partner teams
  • Experienced with Front-End design, DFX and Physical Design Flows
  • Communication skills: excellent oral, written and presentation skills
  • Extensive Experience in handling different PNR tools - Synopsys Fussion, ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
  • Hands on experience on 5nm and sub-5nm projects
  • Experienced in Full Chip Floorplaning, PNR & Partitioning .
  • Experience in Low power and high performance design.
  • Responsible for on-time delivery of block-level layouts with exceptional quality. 
  •  

 

ACADEMIC CREDENTIALS: 

  • 7+ years of experience in Physical Design & FrontEnd Design (synthsis)
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

#LI-ST1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

MTS SILICON DESIGN ENGINEER 

 

THE ROLE: 

AMD is looking for an experienced SOC Physical Design Lead and deliver the next generation of cutting-edge graphics designs. Role includes executing cutting edge Logical and physical implementation actvities 

 

 As part of the RTG SOC team, candidate will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

 

 

THE PERSON: 

  • Strong self-driving ability
  • Strong problem-solving skills with high drive for improvements
  • Should have excellent communication skills (both written and oral)
  • Team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

 

KEY RESPONSIBILITIES: 

  • Responsible for Synthesis, Physical Design, timing and Physical closure
  • Enabling new processes, methodologies and AI driven convervence on PPA
  • Manage a large team of internal and external resources
  • Responsible for ensuring the completion of the SOC chip on schedule with high QOR
  • Physical implementation of block level and subsystem level Next-Gen High Performance Graphics Cores
  • Contribute to Synthesis, Power Reduction, Timing Convergence & Floorplan efforts of block and subsystem

 

PREFERRED EXPERIENCE: 

  • Proven track record on successful Physical implementation execution of complex blocks/SOCs
  • Have an in depth understanding and experience for all  Physical Design activities for a large, leading technology SOC ASIC chip
  • Have strong management, technical problem solving, communication and presentation skills
  • Great team player able to effectively interact and collaborate partner teams
  • Experienced with Front-End design, DFX and Physical Design Flows
  • Communication skills: excellent oral, written and presentation skills
  • Extensive Experience in handling different PNR tools - Synopsys Fussion, ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR
  • Hands on experience on 5nm and sub-5nm projects
  • Experienced in Full Chip Floorplaning, PNR & Partitioning .
  • Experience in Low power and high performance design.
  • Responsible for on-time delivery of block-level layouts with exceptional quality. 
  •  

 

ACADEMIC CREDENTIALS: 

  • 7+ years of experience in Physical Design & FrontEnd Design (synthsis)
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

#LI-ST1

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