Physical Design Engineer

May 31, 2024
Santa Clara, Cuba
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




 

THE ROLE: 

 

The focus of this role is to drive Physical design of critical Graphics blocks on latest architectures, and achieve best-in-class PPA by exploring improvements to RTL, Physical design flows and methodologies.  

 

THE PERSON: 

 

You have a passion for pushing PPA on latest technology nodes and for Physical Design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

 

KEY RESPONSIBILITIES: 

  • Own Physical design closure and PPA attainment for critical Graphics blocks
  • Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
  • Work closely with RTL designers to analyze critical bottlenecks that impact PPA. 
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
  • Drive technical discussions with cross functional teams (Including RTL design, CAD and library teams) to explore optimizations to the design.
  • Technical lead of three to five senior level engineers

 

PREFERRED EXPERIENCE: 

  • ASIC Physical Design from RTL to GDSII
  • Excellent analytical and problem solving skills along with attention to details
  • Strong background in RTL analysis, Timing and Physical Design closure.  
  • Hands on experience in taping out sub 5nm designs. 
  • Expert knowledge and working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
  • Strong communication, Time Management, and Presentation Skills
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion
  • Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

 

Location :

 

Santa Clara, CA

 

#LI-PA1




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 

THE ROLE: 

 

The focus of this role is to drive Physical design of critical Graphics blocks on latest architectures, and achieve best-in-class PPA by exploring improvements to RTL, Physical design flows and methodologies.  

 

THE PERSON: 

 

You have a passion for pushing PPA on latest technology nodes and for Physical Design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

 

 

KEY RESPONSIBILITIES: 

  • Own Physical design closure and PPA attainment for critical Graphics blocks
  • Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
  • Work closely with RTL designers to analyze critical bottlenecks that impact PPA. 
  • Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
  • Drive technical discussions with cross functional teams (Including RTL design, CAD and library teams) to explore optimizations to the design.
  • Technical lead of three to five senior level engineers

 

PREFERRED EXPERIENCE: 

  • ASIC Physical Design from RTL to GDSII
  • Excellent analytical and problem solving skills along with attention to details
  • Strong background in RTL analysis, Timing and Physical Design closure.  
  • Hands on experience in taping out sub 5nm designs. 
  • Expert knowledge and working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
  • Strong communication, Time Management, and Presentation Skills
  • Must be a self-starter, and be able to independently and efficiently drive tasks to completion
  • Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

 

ACADEMIC CREDENTIALS: 

  • Bachelors or Masters degree in computer engineering/Electrical Engineering

 

Location :

 

Santa Clara, CA

 

#LI-PA1

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