Physical Design (front end) Engineer

May 04, 2024
San Diego, Costa Rica
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:

Circuit Technology Server RTL team is looking for passionate and highly experienced Design Engineer for driving FEINT (Front End Integration for Physical Design) for DDR PHY IPs. Be a part of the definition, design and development phase of industry leading and differentiating IPs for various industry protocols as well as proprietary PHYs such as EPYC's infinity data fabric. Work will primarily revolve around working with Architecture team on floor planning, placement, working with RTL designers on timing closure, and being a bridge between RTL and PD teams on various aspects of design work. 

 

Be a part of a team that delivers Industry leading IP and help our experts in RTL, Firmware, circuit and architecture teams develop leading edge and differentiating IPs.

 

 

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

 

 

KEY RESPONSIBILITIES:

  • Work on Floor Planning with Architecture and SOC teams,
  • Drive strategies for place and route for best latency, within the IP and at the IP interface.
  • Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).
  • Work on power optimization with Physical Design teams
  • Be the bridge between Physical Design and RTL teams and also influence technical design decisions for better PPA (power performance architecture). 

 

 PREFERRED EXPERIENCE:

  • Strong foundation in physical design of high speed synthesizable blocks (ASIC design), with industry experience in timing closure and PNR work.
  • Excellent knowledge of PNR (place n route), STA, Primetime, PTPX tool, SDC (synthesis design constraints, CDC.
  • Strong understanding and experience with low level physical phenomena oriented logic design (high speed IO, clocking, Voltage Controlled Oscillators, etc)
  • Strong Analytical, problem solving skills and pronounced attention to detail.
  • Must be self motivated, doing hands on work and must be able to lead by example.
  • Excellent communication and presentation skills.

 

 ACADEMIC CREDENTIALS:

  • Bachelor’s or Master’s degree in related discipline preferred

LOCATION:

Santa Clara, CA

 

 

#LI-HYRBID

#LI-AP3

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

Circuit Technology Server RTL team is looking for passionate and highly experienced Design Engineer for driving FEINT (Front End Integration for Physical Design) for DDR PHY IPs. Be a part of the definition, design and development phase of industry leading and differentiating IPs for various industry protocols as well as proprietary PHYs such as EPYC's infinity data fabric. Work will primarily revolve around working with Architecture team on floor planning, placement, working with RTL designers on timing closure, and being a bridge between RTL and PD teams on various aspects of design work. 

 

Be a part of a team that delivers Industry leading IP and help our experts in RTL, Firmware, circuit and architecture teams develop leading edge and differentiating IPs.

 

 

THE PERSON:

You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

 

 

KEY RESPONSIBILITIES:

  • Work on Floor Planning with Architecture and SOC teams,
  • Drive strategies for place and route for best latency, within the IP and at the IP interface.
  • Work on SDC development, STA (Static Timing)  analysis, shift left of timing closure, CDC (Clock Domain Crossing).
  • Work on power optimization with Physical Design teams
  • Be the bridge between Physical Design and RTL teams and also influence technical design decisions for better PPA (power performance architecture). 

 

 PREFERRED EXPERIENCE:

  • Strong foundation in physical design of high speed synthesizable blocks (ASIC design), with industry experience in timing closure and PNR work.
  • Excellent knowledge of PNR (place n route), STA, Primetime, PTPX tool, SDC (synthesis design constraints, CDC.
  • Strong understanding and experience with low level physical phenomena oriented logic design (high speed IO, clocking, Voltage Controlled Oscillators, etc)
  • Strong Analytical, problem solving skills and pronounced attention to detail.
  • Must be self motivated, doing hands on work and must be able to lead by example.
  • Excellent communication and presentation skills.

 

 ACADEMIC CREDENTIALS:

  • Bachelor’s or Master’s degree in related discipline preferred

LOCATION:

Santa Clara, CA

 

 

#LI-HYRBID

#LI-AP3

 

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