Physical Design Lead-11+ years

Feb 28, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




SMTS - Physical Design (IREM)

 

THE ROLE:

AMD is looking for an experienced SOC Physical IREM Lead to deliver the next generation of cutting-edge graphics designs. 

 

 As part of the RTG SOC team, our team will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how work spaces are setup, how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

 

 

THE PERSON:

  • Strong self-driving ability
  • Strong problem-solving skills with high drive for improvements
  • Should have excellent communication skills (both written and oral)

 

 

 

KEY RESPONSIBILITIES:

  • Lead the team responsible for IREM
  • Drive the overall electrical convergence for high-performance designs.
  • Define the overall electrical analysis methodology (IR analysis, electromigration checks, in-rush analysis), design and/or optimize power grids and power switches for optimal PPA and IR convergence.
  • Work closely with the block owners throughout the project for sign-off electrical convergence.
  • Research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful.

 

 

PREFERRED EXPERIENCE:

  • Proven track record on successfully leading IREM activities  for complex SOC
  • Experience in IR/EM analysis tools and Have an in depth understanding and experience for all  Physical Design activities for a large, leading technology SOC ASIC chip
  • Experience with electrical analysis and convergence including IR drop and power and signal electromigration.
  • Experience with electrical circuit analysis (resistive and RC networks) and basic device physics.
  • Understanding of power-grid design and optimization, and static timing analysis fundamentals.
  • Knowledge of high-performance synthesis and PNR optimizations.
  • Excellent scripting skills with Tcl/Perl.
  •  Proven expertise with packaging centric design and/or electrical analysis towards overall optimization - Co-design expertise across silicon-package-platform Additional Preferred Qualifications: - Experience in Package/Substrate technology development - Exposure to latest industry trends on 3D packaging or product architecture - Working knowledge of design toolsets like Auto CAD, Cadence and/or Mentor Graphics - Familiarity with Package layout extraction and Electrical modeling/simulation tools such as Redhawk-SC
  • Have strong technical problem solving, communication and presentation skills
  • Great team player able to effectively interact and collaborate partner teams
  • Communication skills: excellent oral, written and presentation skills
  • Extensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Hands on experience on  7nm and sub-7nm projects
  • Experience in Low power and high performance design.
  • Responsible for on-time delivery of block-level layouts with exceptional quality.

 

 

 

ACADEMIC CREDENTIALS:

  • 12+ years of experience in Physical Design with atleast 3+ years of experience Lead
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

 

#LI-ST1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS - Physical Design (IREM)

 

THE ROLE:

AMD is looking for an experienced SOC Physical IREM Lead to deliver the next generation of cutting-edge graphics designs. 

 

 As part of the RTG SOC team, our team will be responsible for prioritization and managing the implementation activities on Graphics SOC's. This is built up from basics like how work spaces are setup, how blocks are coordinated and interacted in a System-On-Chip environment, Performance Power Area signoff, how the tools/flows are developed to automate processes. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.

 

 

THE PERSON:

  • Strong self-driving ability
  • Strong problem-solving skills with high drive for improvements
  • Should have excellent communication skills (both written and oral)

 

 

 

KEY RESPONSIBILITIES:

  • Lead the team responsible for IREM
  • Drive the overall electrical convergence for high-performance designs.
  • Define the overall electrical analysis methodology (IR analysis, electromigration checks, in-rush analysis), design and/or optimize power grids and power switches for optimal PPA and IR convergence.
  • Work closely with the block owners throughout the project for sign-off electrical convergence.
  • Research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful.

 

 

PREFERRED EXPERIENCE:

  • Proven track record on successfully leading IREM activities  for complex SOC
  • Experience in IR/EM analysis tools and Have an in depth understanding and experience for all  Physical Design activities for a large, leading technology SOC ASIC chip
  • Experience with electrical analysis and convergence including IR drop and power and signal electromigration.
  • Experience with electrical circuit analysis (resistive and RC networks) and basic device physics.
  • Understanding of power-grid design and optimization, and static timing analysis fundamentals.
  • Knowledge of high-performance synthesis and PNR optimizations.
  • Excellent scripting skills with Tcl/Perl.
  •  Proven expertise with packaging centric design and/or electrical analysis towards overall optimization - Co-design expertise across silicon-package-platform Additional Preferred Qualifications: - Experience in Package/Substrate technology development - Exposure to latest industry trends on 3D packaging or product architecture - Working knowledge of design toolsets like Auto CAD, Cadence and/or Mentor Graphics - Familiarity with Package layout extraction and Electrical modeling/simulation tools such as Redhawk-SC
  • Have strong technical problem solving, communication and presentation skills
  • Great team player able to effectively interact and collaborate partner teams
  • Communication skills: excellent oral, written and presentation skills
  • Extensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk
  • Hands on experience on  7nm and sub-7nm projects
  • Experience in Low power and high performance design.
  • Responsible for on-time delivery of block-level layouts with exceptional quality.

 

 

 

ACADEMIC CREDENTIALS:

  • 12+ years of experience in Physical Design with atleast 3+ years of experience Lead
  • BE/B.Tech/ME/M.TECH or equivalent ECE/EEE

 

 

#LI-ST1

COMPANY JOBS
1739 available jobs
WEBSITE