WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

The Role:

This is an exciting opportunity for a dedicated, hardworking and good team player to join the Physical Design team and work on Full Chip Floorplanning while making a multibillion gates SOC in their latest bleeding edge foundry technology.

Preferred Experience:

• Experience in timing/SDC constraints management. Strong background in Constraint analysis and debug using industry standard tools such as Primetime and DesignCompiler
• Prior experience in chip level floorplanning, feedthrough topology planning, repeater insertion, top level port/pins assignment/alignment and source synchronous bus planning
• Low power design and implementation knowledge on full chip floorplanning.
• Voltage domain check and the DFT Design for Test process

Key Responsibilities:

• Work with Physical Design team on Floor Plan, ram placement, timing closure and resolve various issues including congestion
• Hands on experienced in EDA tools like DC and ICC2
• Hands on experienced in STA tools and technique for timing closure 
• Understanding of floorplan and layout techniques for foundry rule compliant
• Experience in scripting with TCL, Perl or Python
• Good writing, reading and listening skills in English
• Good communication skills with strong interpersonal skills with flexibility

Academic Credentials:

Bachelors or Masters degree in computer engineering/Electrical Engineering plus at least 10 years tapeout and ASIC design experience preferred

#LI-LB1

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

The Role:

This is an exciting opportunity for a dedicated, hardworking and good team player to join the Physical Design team and work on Full Chip Floorplanning while making a multibillion gates SOC in their latest bleeding edge foundry technology.

Preferred Experience:

• Experience in timing/SDC constraints management. Strong background in Constraint analysis and debug using industry standard tools such as Primetime and DesignCompiler
• Prior experience in chip level floorplanning, feedthrough topology planning, repeater insertion, top level port/pins assignment/alignment and source synchronous bus planning
• Low power design and implementation knowledge on full chip floorplanning.
• Voltage domain check and the DFT Design for Test process

Key Responsibilities:

• Work with Physical Design team on Floor Plan, ram placement, timing closure and resolve various issues including congestion
• Hands on experienced in EDA tools like DC and ICC2
• Hands on experienced in STA tools and technique for timing closure 
• Understanding of floorplan and layout techniques for foundry rule compliant
• Experience in scripting with TCL, Perl or Python
• Good writing, reading and listening skills in English
• Good communication skills with strong interpersonal skills with flexibility

Academic Credentials:

Bachelors or Masters degree in computer engineering/Electrical Engineering plus at least 10 years tapeout and ASIC design experience preferred

#LI-LB1