WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.  Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! 

THE PERSON:

• Will excel in leading a team effectively and can manage small to medium sized teams
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a self-starter, and able to independently drive tasks to completion
• Will have good interpersonal skills with a team spirit
• Quality oriented mind set

KEY RESPONSIBILITIES:

• End-to-end design, implementation of complex Analog and Digital PLLs (phase lock loops)
• Run pre-tape out verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

PREFERRED EXPERIENCE:

• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a must: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. 
• Have solid experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
• Scripting languages like Perl, Python, matlab 
• Very fluent with of industry standard tools and practices for analog circuit design
• Preferably has managed small to medium size teams
• Solid knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
• Extensive experience within the semiconductor industry
• Can easily work with industry standard tools and practices for analog circuit design

ACADEMIC CREDENTIALS:

• Master’s in electrical engineering or equivalent is a must, PH.D. preferred

LOCATION:

Vancouver, BC

#LI-AP3

#LI-HYBRID

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

AMD is searching for an experienced Circuit Design Engineer to join the fast-growing PLL design team, responsible for defining, specifying, and implementing current and future advanced PLL IPs powering AMD products.  Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! 

THE PERSON:

• Will excel in leading a team effectively and can manage small to medium sized teams
• Possess strong analytical/problem solving skills and pronounced attention to details
• Must be a self-starter, and able to independently drive tasks to completion
• Will have good interpersonal skills with a team spirit
• Quality oriented mind set

KEY RESPONSIBILITIES:

• End-to-end design, implementation of complex Analog and Digital PLLs (phase lock loops)
• Run pre-tape out verification flows to confirm design meets performance, power, reliability and timing requirements.
• Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution

PREFERRED EXPERIENCE:

• Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm
• Hands-on design experience in performance analog and hybrid Phase Locked Loops, analog-to-digital (ADC), digital-to-analog (DAC) data converter, VCO, LDO, bandgap, charge pump, op-amps, interpolator circuits.
• Experience with the following is a must: Digital PLL techniques, TDC or DSP and control theory experience related to digital PLLs, Dual charge-pump PLL designs, Fractional-N PLLs, spread-spectrum PLLs.
• Proficient with Cadence custom circuit design tools like ADE-L and ADE-XL and running Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis. 
• Have solid experience with simulation tools such as Spectre, Hspice, AFS, and MATLAB, System Verilog, Python.
• Capable of understanding DRC and LVS results with verification tools (Calibre, ICV, or like)
• Scripting languages like Perl, Python, matlab 
• Very fluent with of industry standard tools and practices for analog circuit design
• Preferably has managed small to medium size teams
• Solid knowledge in Physical design, STA, methodology scripts (Tcl), knowledge on Perl, Python
• Extensive experience within the semiconductor industry
• Can easily work with industry standard tools and practices for analog circuit design

ACADEMIC CREDENTIALS:

• Master’s in electrical engineering or equivalent is a must, PH.D. preferred

LOCATION:

Vancouver, BC

#LI-AP3

#LI-HYBRID