PMTS Analog Design Engineer/Lead - GDDR7

Jul 01, 2022
Santa Clara, United States
... Not specified
... Intermediate
Full time
... Office work


What you do at AMD changes everything 
 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 
 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
 

 

PMTS IO Firmware Lead (GDDR)

 

THE ROLE:

We are searching for a Analog engineering lead to join the GDDR PHY design team.  This is an exciting opportunity to lead a team of Analog engineers, responsible for defining, specifying, and implementing custom circuits for training and control for future high-speed GDDR IP and other Memory IO for AMD’s graphics and semi-custom products.

 

THE PERSON:

The successful candidate will possess:

  • Excellent analytical and problem-solving skills along with attention to details
  • Must be a self-starter, able to drive tasks independently and efficiently to completion
  • Strong/effective communication and leadership skills
  • Enthusiastic team-first mentality
  • Ability to provide mentorship and guidance to junior engineers
  • Clearly articulate to Senior Management the development status and challenges
  • Ability to partner with stakeholders (Layout Engineer, Physical Designers, Digital Designers and DV engineers) to develop best practices to improve Operations.
  • Relevant academic background (M. degree preferred) 

 

KEY RESPONSIBILITIES:

  • Lead a group of senior analog engineers to implement and debug circuits for memory I/O
  • Work with design and modeling teams to develop requirements, collaterals, and specifications to support training, power, and feature control
  • Work with Design Verification team to ensure functional correctness
  • Bring-up, optimization, and debug (working with platform and characterization teams)
  • Contribute to hiring of additional engineers
  • Recommend improvements, optimization and power saving enhancements

 

PREFERRED EXPERIENCE:

  • Proven experience in IO analog design from specification to successful silicon
  • Experience in high-speed interfaces such as DDR, GDDR, HBM, and/or high speed SERDES
  • Experience of team leadership
  • Experience with collaterals needed for IO integration
  • Progressive experience in Analog design & development

 

ACADEMIC CREDENTIALS:

  • Relevant academic background (Master’s degree preferred)

 

LOCATION:

Santa Clara, California

Or Folsom, California

 

 

 

#LI-JS3



Requisition Number: 106001 
Country: United States State: California City: Santa Clara 
Job Function: Design
  

 

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