WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

We, AECG ASIC Team at AMD, are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team!

The Role

This role will require deep understanding of design implementation and flows, tools and methodologies, including power intent UPF specifications. This role requires 18+ years of experience in logic design.

• Your expertise in RTL design and coding will enable AMD to meet key goals such as power, performance, and area targets.
• You will collaborate closely with a team of design engineers on a significant project in the early stages.
• Execute on RTL design and coding for various sections of a given IP features, pipeline, and related logic to develop great technology
• Collaborate with other teams assisting with design verification, synthesis, power reduction, timing convergence, and floor planning to realize a great design

The Person

Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as Technical lead/Manager and has a history of achieving quality deliverables meeting schedule in fast pace, Innovation & stakeholder interaction. Basic knowledge of ML, power-performance-Area optimizations, low power designs preferred.

Preferred Skills

• Verilog RTL development experience using industry tools in a CPU, SOC or ASIC environment such that you demonstrate strong facility with:
• Microprocessor architecture, Logic design
• RTL coding experience for a high-speed processor, PCIE, DDR, NVMe, Security, Debug, ARM Core based SS, NoC
• Power saving techniques
• Strong problem solving and debugging skills
• Your commitment to innovating as a team as shown through excellent communication, knowledge of proper documentation techniques, and a track record of independently driving tasks to completion
• Breadth as well as depth as evidenced by exposure to physical design and verification methods and awareness of synthesis, place and route, and timing closure concepts
• RTL design and debug of relevant blocks to realize the low power architecture in silicon.

• Work with verification and physical design teams to achieve high quality design and successful tape out
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas.
• Perform RTL-Level design verification and debugging as needed.

Additional Experience Desired

• 18+ years of Strong design expertise in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex IP like CPU/GPU etc..
• Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
• Expertise in Low power digital design and analysis. Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
• Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
• hands-on with TCL, Perl, Python scripting,
• Strong verbal and written communication skills

• Ability to organize and present complex technical information
• Background in other aspects of ASIC implementation, especially with synthesis flow, static timing analysis (STA), and power flow (PTPX) will be a plus.
• Knowledge of microprocessor design-for-test (DFT) and design-for-debug (DFD) logic will be a plus.
• Experience in clocking, reset, power-up sequences and power management
• Experience with x86 architecture, ARM or any other industry standard microprocessor ISA.
• Working knowledge of C/C++/System Verilog/UVM with verif background will be a plus.

Academic Credentials

• Bachelors or Masters degree in Electronics & Communication Engineering/Electrical Engineering

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

We, AECG ASIC Team at AMD, are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team!

The Role

This role will require deep understanding of design implementation and flows, tools and methodologies, including power intent UPF specifications. This role requires 18+ years of experience in logic design.

• Your expertise in RTL design and coding will enable AMD to meet key goals such as power, performance, and area targets.
• You will collaborate closely with a team of design engineers on a significant project in the early stages.
• Execute on RTL design and coding for various sections of a given IP features, pipeline, and related logic to develop great technology
• Collaborate with other teams assisting with design verification, synthesis, power reduction, timing convergence, and floor planning to realize a great design

The Person

Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as Technical lead/Manager and has a history of achieving quality deliverables meeting schedule in fast pace, Innovation & stakeholder interaction. Basic knowledge of ML, power-performance-Area optimizations, low power designs preferred.

Preferred Skills

• Verilog RTL development experience using industry tools in a CPU, SOC or ASIC environment such that you demonstrate strong facility with:
• Microprocessor architecture, Logic design
• RTL coding experience for a high-speed processor, PCIE, DDR, NVMe, Security, Debug, ARM Core based SS, NoC
• Power saving techniques
• Strong problem solving and debugging skills
• Your commitment to innovating as a team as shown through excellent communication, knowledge of proper documentation techniques, and a track record of independently driving tasks to completion
• Breadth as well as depth as evidenced by exposure to physical design and verification methods and awareness of synthesis, place and route, and timing closure concepts
• RTL design and debug of relevant blocks to realize the low power architecture in silicon.

• Work with verification and physical design teams to achieve high quality design and successful tape out
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
• Collaborate with cross-functional teams to solve novel problems across multiple functional areas.
• Perform RTL-Level design verification and debugging as needed.

Additional Experience Desired

• 18+ years of Strong design expertise in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex IP like CPU/GPU etc..
• Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
• Expertise in Low power digital design and analysis. Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
• Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
• hands-on with TCL, Perl, Python scripting,
• Strong verbal and written communication skills

• Ability to organize and present complex technical information
• Background in other aspects of ASIC implementation, especially with synthesis flow, static timing analysis (STA), and power flow (PTPX) will be a plus.
• Knowledge of microprocessor design-for-test (DFT) and design-for-debug (DFD) logic will be a plus.
• Experience in clocking, reset, power-up sequences and power management
• Experience with x86 architecture, ARM or any other industry standard microprocessor ISA.
• Working knowledge of C/C++/System Verilog/UVM with verif background will be a plus.

Academic Credentials

• Bachelors or Masters degree in Electronics & Communication Engineering/Electrical Engineering

#LI-LL1

#LI-HYBRID