WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

We are seeking a seasoned Verification technical lead  with expertise or significant interest in Finding Verification Solutions. You have had significant success driving the full verification cycle including test plan development, testbench development, automation of test bench using scripts and ensuring milestone dates are met as scheduled. You are meticulous about all verification metrics while driving schedule and managing cost. This senior role will stretch you as you mentor verification teams in new directions, network with our world-class, very experienced verification minds, and negotiate amongst design teams and architecture teams.
THE PERSON:

You have excellent communication and presentation skills. You have self-driving capability and problem-solving skills.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Candidate is expected to be a strong team player with good communication and leadership skills
• Experience with development of UVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
• Experience on bus protocols, inter-die interface/communication. Worked on Block/Sub-system level environment, VIP development is an added advantage.
• Familiar with PCIE, AXI, AMBA. UFS, Ethernet bus protocols
• Experience with Python / Perl or any other scripting language is a plus
• Experience with gate-level simulation, co-sim power verification, reset verification, contention checking is desired

 PREFERRED EXPERIENCE:

• Provide technical leadership and contribution Block and Subsystem level verification
• Develop advanced System Verilog and UVM based testbench and Automation scripts that can scale with Full-Chip which enables improved quality and execution
• Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior verification Leads with strong interpersonal skills to work across teams in different geographies

 ACADEMIC CREDENTIALS:

• BS/MS degree in Electrical/Computer engineering

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

We are seeking a seasoned Verification technical lead  with expertise or significant interest in Finding Verification Solutions. You have had significant success driving the full verification cycle including test plan development, testbench development, automation of test bench using scripts and ensuring milestone dates are met as scheduled. You are meticulous about all verification metrics while driving schedule and managing cost. This senior role will stretch you as you mentor verification teams in new directions, network with our world-class, very experienced verification minds, and negotiate amongst design teams and architecture teams.
THE PERSON:

You have excellent communication and presentation skills. You have self-driving capability and problem-solving skills.  You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

• Candidate is expected to be a strong team player with good communication and leadership skills
• Experience with development of UVM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification
• Experience on bus protocols, inter-die interface/communication. Worked on Block/Sub-system level environment, VIP development is an added advantage.
• Familiar with PCIE, AXI, AMBA. UFS, Ethernet bus protocols
• Experience with Python / Perl or any other scripting language is a plus
• Experience with gate-level simulation, co-sim power verification, reset verification, contention checking is desired

 PREFERRED EXPERIENCE:

• Provide technical leadership and contribution Block and Subsystem level verification
• Develop advanced System Verilog and UVM based testbench and Automation scripts that can scale with Full-Chip which enables improved quality and execution
• Test Planning, testbench architecture, execution, tracking, coverage closure, and delivery to programs
• Excellent communication, management, and presentation skills.
• Adept at collaboration among top-thinkers and senior verification Leads with strong interpersonal skills to work across teams in different geographies

 ACADEMIC CREDENTIALS:

• BS/MS degree in Electrical/Computer engineering