PMTS Silicon Design Engineer

Mar 07, 2024
Bengaluru, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




PMTS SILICON DESIGN ENGINEER

 

THE ROLE:

The AMD IOHUB Team (part of the NBIO organization) is looking for an PMTS Silicon Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution.

As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

 

THE PERSON:

A successful candidate will work with senior silicon design engineers, architects, RTL writers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

 

KEY RESPONSIBLITIES:

Understanding architecture and micro-architecture features of AMD’s next generation IPs in SoCs.
Strong experience in complex ASIC IP Designs with focus on high performance, low area, and low power. Position requires thorough knowledge of ASIC design flow
Design and develop interface logic with best PPA in complex IP environment.
Well versed and hands-on with design methodologies and EDA tools for DFT,power,clocking and debug.
Analyze proposed specifications to understand implementation challenges and opportunities, working with the architects to improve and refine the ideas.
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Knowledge sharing and other contributions to Platform & System Architecture (Experience in Memory management Unit in SOCs is preferred)
Expertise in Secure Boot, IP/SoC Security, Threat Modelling, security Hackathons.
Define product features and capabilities, close architecture and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams.
Comprehend the SoC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power.
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Knowledge sharing and other contributions to Platform & System Architecture
As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.
Conduct design reviews of designers in technical presentations to peers and top management.
Oversees Synthesis and netlist delivery that meets PPA bounding box. Assist physical design team on the floor-planning and timing closure.
Work with Design & Verification team to ensure quality for architecture definition and design implementation.
Preferred to have some people management experience. Possess the skill of mentoring and coaching the RTL Design team.
Should be proactive in adopting new RTL Design and Verification methodologies prevailing in the industry.
Working with Architects/RTL team for optimizing and features for maximum new features and performance gains and correlating the features on RTL.
Strong sense of task ownership, scheduling and deliver on time for committed milestones.

 

PREFERRED EXPERIENCE:

Strong knowledge of computer architecture with good experience of working and developing microarchitectural.
Knowledge of python or some other scripting language
Knowledge of Verilog/VHDL
Experience in data and control path design in PCIe/High-Speed DMAs.
Expert on Verilog/VHTDL RTL design and has experience of large digital SoC project.
Complex Sub-System Micro-Architecture, RTL Implementation, Static checks and taking module to the tape-out.
Comprehensive knowledge and exposure to various front-end and physical design EDA tools and flows.
Familiar with Unix/Linux and scripts (tcl, perl, ruby etc.)

 


ACADEMIC CREDENTIALS:

Bachelor’s or master’s or PhD. degree in computer engineering/computer science

#LI-PS1




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

PMTS SILICON DESIGN ENGINEER

 

THE ROLE:

The AMD IOHUB Team (part of the NBIO organization) is looking for an PMTS Silicon Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution.

As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

 

THE PERSON:

A successful candidate will work with senior silicon design engineers, architects, RTL writers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

 

KEY RESPONSIBLITIES:

Understanding architecture and micro-architecture features of AMD’s next generation IPs in SoCs.
Strong experience in complex ASIC IP Designs with focus on high performance, low area, and low power. Position requires thorough knowledge of ASIC design flow
Design and develop interface logic with best PPA in complex IP environment.
Well versed and hands-on with design methodologies and EDA tools for DFT,power,clocking and debug.
Analyze proposed specifications to understand implementation challenges and opportunities, working with the architects to improve and refine the ideas.
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Knowledge sharing and other contributions to Platform & System Architecture (Experience in Memory management Unit in SOCs is preferred)
Expertise in Secure Boot, IP/SoC Security, Threat Modelling, security Hackathons.
Define product features and capabilities, close architecture and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams.
Comprehend the SoC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power.
Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements.
Knowledge sharing and other contributions to Platform & System Architecture
As an overall product owner, responsible for architecture analysis and technical solutions for marketing/feature change requests
Work closely with Design teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
Support Post-Si teams for Product Performance, Power and functional issues debug/resolution.
Conduct design reviews of designers in technical presentations to peers and top management.
Oversees Synthesis and netlist delivery that meets PPA bounding box. Assist physical design team on the floor-planning and timing closure.
Work with Design & Verification team to ensure quality for architecture definition and design implementation.
Preferred to have some people management experience. Possess the skill of mentoring and coaching the RTL Design team.
Should be proactive in adopting new RTL Design and Verification methodologies prevailing in the industry.
Working with Architects/RTL team for optimizing and features for maximum new features and performance gains and correlating the features on RTL.
Strong sense of task ownership, scheduling and deliver on time for committed milestones.

 

PREFERRED EXPERIENCE:

Strong knowledge of computer architecture with good experience of working and developing microarchitectural.
Knowledge of python or some other scripting language
Knowledge of Verilog/VHDL
Experience in data and control path design in PCIe/High-Speed DMAs.
Expert on Verilog/VHTDL RTL design and has experience of large digital SoC project.
Complex Sub-System Micro-Architecture, RTL Implementation, Static checks and taking module to the tape-out.
Comprehensive knowledge and exposure to various front-end and physical design EDA tools and flows.
Familiar with Unix/Linux and scripts (tcl, perl, ruby etc.)

 


ACADEMIC CREDENTIALS:

Bachelor’s or master’s or PhD. degree in computer engineering/computer science

#LI-PS1

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