WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

PMTS SILICON DESIGN ENGINEER

THE ROLE:

A great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as a Sr. Staff Engineer / Principal Member of Technical Staff.

KEY RESPONSIBILITIES:

• Senior-level lead engineer driving SIGNOFF (FCT, IR/EM,power profiling, RDL) teams improvements in both pre-silicon and post-silicon design phase
• Tasks to include  Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off.
• Drive cross-functional teams  (technology,  CAD tools,  platform characterization, binning  practices, and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt
• Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
• Drive and hands-on flow development and scripting
• Drive silicon correlation and  deliver  systematic improvements to improve silicon to STA on high-performance Graphics IP

KEY REQUIREMENTS:

• Excellent analytical and problem-solving skills along with attention to details
• Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
• Knowledge of Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations will be plus.
• Hands on experience in taping out  7nm, 10nm, and 28nm SOC
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
• Strong communication, Time Management, and Presentation Skills
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

EDUCATION:

• BSEE/BSCS OR MSEE/MSCE preferred
• Prior experience in ASIC Physical Design from RTL to GDSII

If you have the above-required skills and are looking for a career opportunity to step up, this is the position for you. Join us and lead the world together.

#LI-PH1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

PMTS SILICON DESIGN ENGINEER

THE ROLE:

A great opportunity to be part of the next generation GPU chip development team at AMD Santa Clara for ASIC Physical Design engineer. You will join us as a Sr. Staff Engineer / Principal Member of Technical Staff.

KEY RESPONSIBILITIES:

• Senior-level lead engineer driving SIGNOFF (FCT, IR/EM,power profiling, RDL) teams improvements in both pre-silicon and post-silicon design phase
• Tasks to include  Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off.
• Drive cross-functional teams  (technology,  CAD tools,  platform characterization, binning  practices, and design methodology) and optimize margining practices across boundaries to deliver best in class performance/watt
• Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
• Drive and hands-on flow development and scripting
• Drive silicon correlation and  deliver  systematic improvements to improve silicon to STA on high-performance Graphics IP

KEY REQUIREMENTS:

• Excellent analytical and problem-solving skills along with attention to details
• Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
• Knowledge of Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations will be plus.
• Hands on experience in taping out  7nm, 10nm, and 28nm SOC
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
• Strong communication, Time Management, and Presentation Skills
• Must be a self-starter, and be able to independently and efficiently drive tasks to completion
• Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player

EDUCATION:

• BSEE/BSCS OR MSEE/MSCE preferred
• Prior experience in ASIC Physical Design from RTL to GDSII

If you have the above-required skills and are looking for a career opportunity to step up, this is the position for you. Join us and lead the world together.

#LI-PH1