PPA Physical Design Engineer

Jan 31, 2024
San Jose, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER

 

THE ROLE:

AMD is looking for an engineer passionate about driving the best Power Performance Area (PPA) of AMD’s AI Accelerators for client, server, and adaptable silicon devices. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AI.

 

THE PERSON:

The ideal candidate should have demonstrated experience in physical design optimization and understand the tradeoffs involved during the design process. Able to communicate effectively and work optimally with different teams across AMD.  

 

KEY RESPONSIBILITIES:

  1. Will be part of a small team building recipes to maximize PPA for our AI blocks.
  2. In this role, we will be collaborating with the front-end, SoC and CAD groups to make our AI cores the best in the industry.
  3. You will be responsible for block construction from synthesis to route and timing analysis for our IP blocks.
  4. You will be working on floor planning, pin-placement and macro placements to reduce congestion and improve utilization.
  5. You will be collaborating with the front-end team on timing and power and recommending improvements.
  6. Assist in flow modifications to improve runtimes.  

 

PREFERRED EXPERIENCE:

  1. Deep experience of Synthesis, Place & Route, CTS, timing, physical and EMIR closure.
  2. Strong knowledge of floor-planning, pin assignment, extraction and STA methodology and tools.
  3. Strong understanding of the PPA tradeoffs in physical design.
  4. Proven track record of taping out chips in 7nm and below.     
  5. Strong scripting skills (tcl, perl, python etc)
  6. Knowledge of structured placements of gates is a plus.
  7. Experience in low-power methodology is a plus.  

 

ACADEMIC CREDENTIALS:

BS or MS in Electrical Engineering, with 10+ years of relevant experience. 

 

LOCATION:

San Jose CA

 

 

#LI-EM1

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

 

THE ROLE:

AMD is looking for an engineer passionate about driving the best Power Performance Area (PPA) of AMD’s AI Accelerators for client, server, and adaptable silicon devices. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. You will be a member of a core team of incredibly talented industry specialists and will work with the latest and rapidly evolving hardware technologies for AI.

 

THE PERSON:

The ideal candidate should have demonstrated experience in physical design optimization and understand the tradeoffs involved during the design process. Able to communicate effectively and work optimally with different teams across AMD.  

 

KEY RESPONSIBILITIES:

  1. Will be part of a small team building recipes to maximize PPA for our AI blocks.
  2. In this role, we will be collaborating with the front-end, SoC and CAD groups to make our AI cores the best in the industry.
  3. You will be responsible for block construction from synthesis to route and timing analysis for our IP blocks.
  4. You will be working on floor planning, pin-placement and macro placements to reduce congestion and improve utilization.
  5. You will be collaborating with the front-end team on timing and power and recommending improvements.
  6. Assist in flow modifications to improve runtimes.  

 

PREFERRED EXPERIENCE:

  1. Deep experience of Synthesis, Place & Route, CTS, timing, physical and EMIR closure.
  2. Strong knowledge of floor-planning, pin assignment, extraction and STA methodology and tools.
  3. Strong understanding of the PPA tradeoffs in physical design.
  4. Proven track record of taping out chips in 7nm and below.     
  5. Strong scripting skills (tcl, perl, python etc)
  6. Knowledge of structured placements of gates is a plus.
  7. Experience in low-power methodology is a plus.  

 

ACADEMIC CREDENTIALS:

BS or MS in Electrical Engineering, with 10+ years of relevant experience. 

 

LOCATION:

San Jose CA

 

 

#LI-EM1

 

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