WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE: 

AMD’s Low Power Advanced Development team is seeking talented, self-motivated individuals to help develop low power innovations that enable industry-leading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects. 

THE PERSON:

A candidate who is seeking challenging projects in low power design using the latest modern semiconductor technologies, who is eager to learn and is a good team player.

KEY RESPONSIBILITIES:

• Working on low power management system design for CPU and GPU applications, custom mixed-signal circuits and logic design in advanced CMOS technologies using custom and semi-custom physical design flows
• Design and Simulate Power Management Circuit Architectures on System level, RTL level and on Transistor level using Matlab, SystemVerilog, Verilog, Verilog-A and Hspice
• Develop and Simulate RTL code in Verilog
• Design, simulate, and verify analog mixed-signal circuits including system level in HSpice
• Design mixed-signal architectures for optimum power/speed/area efficiency
• Closely work with SOC system architects to define mixed-signal design specifications
• Closely work with Platform architects and Packaging team for Power Integrity and Power Distribution Network analysis in mixed-signal design applications
• Closely work with and supervise layout/mask designers by providing annotated schematics, floor plans, layout, reliability and manufacturability design guidelines
• Experience in back-end design verification tools and flows including debugging LVS and DRC issues in collaboration with the layout team
• Work in collaboration with Physical Design Engineers on mixed-signal design chip level planning and integration
• Create or in collaboration with other team members design reviews, technical reports, and other documentation required for meeting the design quality and for the tapeout signoff

PREFERRED EXPERIENCE:

• Requires strong understanding of analog/mixed signal design concepts, CMOS processes, Package architecture and Chip integration on PCB
• Must be an expert in Verilog. VCS/Verdi experience is highly desired.
• Knowledge of basic analog blocks: Linear and Switching voltage regulators, DAC, ADC, comparators, oscillators, high speed clock circuits
• Strong knowledge in Matlab, Verilog-A, Verilog and SystemVerilog
• Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools
• Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF
• Good experience in Synopsys based mixed-signal co-simulation flow
• Scripting: C, python, perl, csh. Experience with TCL is a plus
• Knowledge in the digital design flows
• Strong communication skills, teamwork experience and a quick learner in a fast-moving environment

ACADEMIC CREDENTIALS: 

• PhD/MS w/ 10+ years experience in Electrical Engineering
• Computer Architecture work experience

LOCATION: Markham, Canada

#LI-TB2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

AMD’s Low Power Advanced Development team is seeking talented, self-motivated individuals to help develop low power innovations that enable industry-leading power efficient computing and graphics products. We have openings for R&D engineers to serve as key contributors in small project teams working on low power advanced development projects. 

THE PERSON:

A candidate who is seeking challenging projects in low power design using the latest modern semiconductor technologies, who is eager to learn and is a good team player.

KEY RESPONSIBILITIES:

• Working on low power management system design for CPU and GPU applications, custom mixed-signal circuits and logic design in advanced CMOS technologies using custom and semi-custom physical design flows
• Design and Simulate Power Management Circuit Architectures on System level, RTL level and on Transistor level using Matlab, SystemVerilog, Verilog, Verilog-A and Hspice
• Develop and Simulate RTL code in Verilog
• Design, simulate, and verify analog mixed-signal circuits including system level in HSpice
• Design mixed-signal architectures for optimum power/speed/area efficiency
• Closely work with SOC system architects to define mixed-signal design specifications
• Closely work with Platform architects and Packaging team for Power Integrity and Power Distribution Network analysis in mixed-signal design applications
• Closely work with and supervise layout/mask designers by providing annotated schematics, floor plans, layout, reliability and manufacturability design guidelines
• Experience in back-end design verification tools and flows including debugging LVS and DRC issues in collaboration with the layout team
• Work in collaboration with Physical Design Engineers on mixed-signal design chip level planning and integration
• Create or in collaboration with other team members design reviews, technical reports, and other documentation required for meeting the design quality and for the tapeout signoff

PREFERRED EXPERIENCE:

• Requires strong understanding of analog/mixed signal design concepts, CMOS processes, Package architecture and Chip integration on PCB
• Must be an expert in Verilog. VCS/Verdi experience is highly desired.
• Knowledge of basic analog blocks: Linear and Switching voltage regulators, DAC, ADC, comparators, oscillators, high speed clock circuits
• Strong knowledge in Matlab, Verilog-A, Verilog and SystemVerilog
• Cadence's custom IC design environment with special emphasis on Virtuoso schematic/layout design entry tools
• Analog/mixed signal circuit simulators, specifically Hspice, Spectre, SpectreRF
• Good experience in Synopsys based mixed-signal co-simulation flow
• Scripting: C, python, perl, csh. Experience with TCL is a plus
• Knowledge in the digital design flows
• Strong communication skills, teamwork experience and a quick learner in a fast-moving environment

ACADEMIC CREDENTIALS: 

• PhD/MS w/ 10+ years experience in Electrical Engineering
• Computer Architecture work experience

LOCATION: Markham, Canada

#LI-TB2