Senior Design Verification Engineer - 162001
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
Design Verification Engineer
This role is for AMD’s next generation state of art high speed IOs (PHYs) verification. We are looking for logic verification for mixed signal group developing differentiating IP for AMD's processor and graphic products. You will be interacting with a team of smart analog and digital designers and verification engineers, building complex testbenches analog/digital/FW IPs and make sure that design is bug free.
We seek an expert verification engineer who has knowledge of UVM, SystemVerilog, debugging skills. Candidate should be self-driven, with great sense of ownership. You must be a strong and effective communicator, both verbal and written, which are essential when working with a globally distributed team.
- Once on board, you will work closely with assigned mentor to ramp up on our various protocols about high speed, and various parts of our verification.
- It is expected to own a full block in six months. You will also learn about analog verification and firmware verification.
- Must be a team player with a commitment to meeting deadlines and an aptitude to thrive in a fast-paced multi-tasking environment.
- Responsible for effective communication across organizations/levels for program status update (both working details to the team, and executive summary for Executive communication).
- Implementing and Managing changes and interventions to ensure project goals are achieved.
- Developing new programs to support the strategic direction of the organization.
Preferred Skills & Experience
- Focus on Logic Design, Computer Architecture and 9+ years of industry experience in Design Verification.
- Hands-on experience in UVM, System Verilog logic, Verilog design and verification
- Hands-on experience in Formal Verification and related tools
- Hands-on experience with low power design and power analysis flows
- Familiar with languages like Perl, C/C++ etc.
- Work well with others in a team environment
- Communicate technical details with team members both on-site and remotely
- Conduct design reviews of designs in technical presentations to peers and management
- Strong candidates may also have SERDES (PCIe, SATA, USB) experience, high level understanding of analog and mixed signal circuits, and experience with mixed signal simulators.
- Experience in managing horizontally across multiple internal functional organization.
- The applicant must be a team player with a commitment to meeting deadlines/Lead & Drive for solutions and an aptitude to thrive in a fast-paced multi-tasking environment.
- Creative, Self-Driven, highly motivated individual with demonstrated ability to independently manage complex engineering tasks.
- Strong interpersonal communication, analytical, project management, task & time management, and excellent executive communication skills.
Academic Credentials: BS in electrical/electronic/computer-science or related field is required; Master's degree preferred
Location: Santa Clara, CA (Other locations available)
Requisition Number: 162001
Country: United States State: California City: Santa Clara
Job Function: Design
Benefits offered are described here.
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