WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

THE ROLE:

This is an exciting opportunity to work in the AMD SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and participate in silicon bring up.

THE PERSON:

We are looking for a dynamic candidate who will have great opportunity to work on the state of the art products with leading verification methodology. Take your current verification  expertise and apply that to state of the are data center products involving complex protocols like PCIE, CXL, networking etc

 KEY RESPONSIBILITIES:

• Create block level verification plan, test plans and full chip test plan
• Develop block level test bench and tests in UVM methodology including scoreboard.
• Work on subsystem level verification
• Work with designers to get the coverage closure
• Port the block level tests to full chip test bench
• Integrate VIPs as needed
• Work with software, validation and emulation teams as needed
• Work on other aspects of verification like CDC, gate simulation
• Work on power aware verification using UPF
• Work on lab bring up and silicon validation

PREFERRED EXPERIENCE:

• Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
• Good understanding of object-oriented programming concepts
• Prior experience with PCIE Protocol Gen3 and above
• Prior experience in verifying is system/sub system level involving multiple blocks
• Prior experience with protocols such as AXI, APB, AHB etc
• Programming in scripting languages like Python, TCL and Perl
• Excellent communication skills
• Good problem-solving skills and analytical ability
• Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.

ACADEMIC CREDENTIALS:

• BS minimum Masters preferred Computer Engineering Computer Science

LOCATION:

San Jose, CA

#LI-EW1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

This is an exciting opportunity to work in the AMD SOC Verification Team as Senior Verification Engineer. The candidate will have an opportunity to work on state-of-the-art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and participate in silicon bring up.

THE PERSON:

We are looking for a dynamic candidate who will have great opportunity to work on the state of the art products with leading verification methodology. Take your current verification  expertise and apply that to state of the are data center products involving complex protocols like PCIE, CXL, networking etc

 KEY RESPONSIBILITIES:

• Create block level verification plan, test plans and full chip test plan
• Develop block level test bench and tests in UVM methodology including scoreboard.
• Work on subsystem level verification
• Work with designers to get the coverage closure
• Port the block level tests to full chip test bench
• Integrate VIPs as needed
• Work with software, validation and emulation teams as needed
• Work on other aspects of verification like CDC, gate simulation
• Work on power aware verification using UPF
• Work on lab bring up and silicon validation

PREFERRED EXPERIENCE:

• Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology
• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
• Good understanding of object-oriented programming concepts
• Prior experience with PCIE Protocol Gen3 and above
• Prior experience in verifying is system/sub system level involving multiple blocks
• Prior experience with protocols such as AXI, APB, AHB etc
• Programming in scripting languages like Python, TCL and Perl
• Excellent communication skills
• Good problem-solving skills and analytical ability
• Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.

ACADEMIC CREDENTIALS:

• BS minimum Masters preferred Computer Engineering Computer Science

LOCATION:

San Jose, CA

#LI-EW1