WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

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THE ROLE:

Senior DFT manager will lead strong engineering team on Scan, MBIST, iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The IPs range from complex processor, AI computation block, to state-of-the-art controller IPs which provide automotive, data centre, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will get opportunity to expand technical knowledge beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for FPGA and deep silicon debug work all the way to high-volume production requirement. This is the role to oversee complete silicon cycle from design to production phases.

THE PERSON:

We are looking for candidate that can communicate complex engineering subject effectively to technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful senior manager will interact with many external teams and must confidently represent his/her organization.

KEY RESPONSIBILITIES:

• Manage DFT engineers resolving technical challenges and meeting product schedule
• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
• Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG
• Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle
• Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

PREFERRED EXPERIENCE:

• Over 7 years of DFT engineering management experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Strong MBIST knowledge
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills, works well in a group environment that spans across continents
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc

ACADEMIC CREDENTIALS:

• MS or Ph.D. in Electrical/Electronic/Computer Engineering

LOCATION:

Singapore

#LI-SP2

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

Senior DFT manager will lead strong engineering team on Scan, MBIST, iJTAG test development of latest 7nm MPSoC (Multi Processor System on Chip) products and beyond. The IPs range from complex processor, AI computation block, to state-of-the-art controller IPs which provide automotive, data centre, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly inserted, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will get opportunity to expand technical knowledge beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for FPGA and deep silicon debug work all the way to high-volume production requirement. This is the role to oversee complete silicon cycle from design to production phases.

THE PERSON:

We are looking for candidate that can communicate complex engineering subject effectively to technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful senior manager will interact with many external teams and must confidently represent his/her organization.

KEY RESPONSIBILITIES:

• Manage DFT engineers resolving technical challenges and meeting product schedule
• Work closely with design team and make sure DFT structures are correctly inserted.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in FPGAs.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
• Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, 1149.1 JTAG and IJTAG
• Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle
• Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management

PREFERRED EXPERIENCE:

• Over 7 years of DFT engineering management experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Strong MBIST knowledge
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills, works well in a group environment that spans across continents
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc

ACADEMIC CREDENTIALS:

• MS or Ph.D. in Electrical/Electronic/Computer Engineering

LOCATION:

Singapore

#LI-SP2