WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE: 

Circuit Technology team is looking for a passionate and experienced DFT Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs. This opportunity includes ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup. Be a part of a team that delivers Industry leading IPs that touch every single SOC delivered by AMD. 

THE PERSON:

Have strong analytical/problem-solving skills and pronounced attention to details. Must be able to execute hands-on, a self-starter, a leader, and be able to independently drive tasks to completion.

KEY RESPONSIBLITIES:

• Lead and define PHY specific Design for Test/Debug/Yield Features.
• Implementation of DFX features into RTL using verilog.
• Understanding of DFX Architectures and micro-architectures.
• Experience with JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Spyglass bringup and analysis for scan readiness/test coverage gaps.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Support silicon bring-up and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows.

PREFERRED EXPERIENCE:

• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with industry standard DFX methodology: e.g Streaming Scan Network (aka SSN), IJTAG, ICL/PDL etc
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

ACADEMIC CREDENTIALS:

• BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques.

 LOCATION: Santa Clara,  Austin

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE: 

Circuit Technology team is looking for a passionate and experienced DFT Methodology/Architect/RTL execution Lead for the high-speed SERDES Phys, Next gen Memory Phys and Die-to-Die interconnect IPs. This opportunity includes ownership of defining the DFX architecture for high-speed PHYs as well as die-to die connectivity IP designs, RTL coding, supporting scan stitching, timing constraints development, supporting ATPG as well as post-silicon bringup. Be a part of a team that delivers Industry leading IPs that touch every single SOC delivered by AMD. 

THE PERSON:

Have strong analytical/problem-solving skills and pronounced attention to details. Must be able to execute hands-on, a self-starter, a leader, and be able to independently drive tasks to completion.

KEY RESPONSIBLITIES:

• Lead and define PHY specific Design for Test/Debug/Yield Features.
• Implementation of DFX features into RTL using verilog.
• Understanding of DFX Architectures and micro-architectures.
• Experience with JTAG (1149.1/1687/1500)/IJTAG, Scan Compression (EDT, SSH), and at-speed scan testing implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Spyglass bringup and analysis for scan readiness/test coverage gaps.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Support silicon bring-up and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows.

PREFERRED EXPERIENCE:

• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with industry standard DFX methodology: e.g Streaming Scan Network (aka SSN), IJTAG, ICL/PDL etc
• Familiarity with SystemVerilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clock gates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

ACADEMIC CREDENTIALS:

• BS/MS/PhD in EE/ECE/CE/CS with industry experience in advanced DFx techniques.

 LOCATION: Santa Clara,  Austin

#LI-TB2

#HYBRID