Senior Principal Technical Lead - RTL Architecture and Design

May 11, 2024
Santa Clara, Cuba
... Not specified
... Senior
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_




THE ROLE:   

The candidate will be part of AMD memory interfaces design group, responsible for defining, specifying, architecting, executing and productizing leading-edge memory PHYs for future SOCs.

 

KEY RESPONSIBILITIES: 

  • Technical leadership and technical direction setting for whole memory PHY RTL team.
  • Working with customers and consumers to understand feature requirements and translate them into implementable specs
  • Definition of RTL architecture, microarchitecture, and design implementation of memory PHYs
  • Documentation of RTL architecture and micro-architecture
  • RTL coding, code reviews and debug
  • Setting and enforcing quality standard for RTL development
  • Engagement in Post-Silicon activities such as Bring-Up, Platform Validation, Characterization, Parameters Optimization and final Productization
  • Support the definition of development flows that improve efficiency and quality of execution.
  • Work closely with Physical Design, Firmware and Design Verification to ensure successful end-to-end RTL implementation.  

 

REQUIREMENTS: 

  • A proven record of successful tape-outs and IPs productization, preferrably in high-speed IPs (Memory or Serdes)
  • Ability to translate a product feature description into an implementable architecture/design that may include RTL and or Firmware, including clear documentation enabling the implementation and verification of the design.
  • Skill and experience in guiding teams at a technical level and working with external groups to understand requirements and devise/negotiate workable solutions to inter-IP challenges. 
  • Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices.
  • Understanding of and experience in refactoring/restructuring designs to solve timing/area challenges.  Includes algorithmic and structural design changes.
  • Experience and understanding of optimizing hardware vs firmware implementation for overall product performance/efficiency.
  • Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL design (front-end and back-end) and Design Verification

 

 

ACADEMIC CREDENTIALS: 

MSEE + or PhD 

 

#LI-AP3

#LI-HYBRID




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:   

The candidate will be part of AMD memory interfaces design group, responsible for defining, specifying, architecting, executing and productizing leading-edge memory PHYs for future SOCs.

 

KEY RESPONSIBILITIES: 

  • Technical leadership and technical direction setting for whole memory PHY RTL team.
  • Working with customers and consumers to understand feature requirements and translate them into implementable specs
  • Definition of RTL architecture, microarchitecture, and design implementation of memory PHYs
  • Documentation of RTL architecture and micro-architecture
  • RTL coding, code reviews and debug
  • Setting and enforcing quality standard for RTL development
  • Engagement in Post-Silicon activities such as Bring-Up, Platform Validation, Characterization, Parameters Optimization and final Productization
  • Support the definition of development flows that improve efficiency and quality of execution.
  • Work closely with Physical Design, Firmware and Design Verification to ensure successful end-to-end RTL implementation.  

 

REQUIREMENTS: 

  • A proven record of successful tape-outs and IPs productization, preferrably in high-speed IPs (Memory or Serdes)
  • Ability to translate a product feature description into an implementable architecture/design that may include RTL and or Firmware, including clear documentation enabling the implementation and verification of the design.
  • Skill and experience in guiding teams at a technical level and working with external groups to understand requirements and devise/negotiate workable solutions to inter-IP challenges. 
  • Thorough understanding of multiple clock/reset/power domain design challenges and safe/robust design practices.
  • Understanding of and experience in refactoring/restructuring designs to solve timing/area challenges.  Includes algorithmic and structural design changes.
  • Experience and understanding of optimizing hardware vs firmware implementation for overall product performance/efficiency.
  • Excellent knowledge of industry-standard tools and best-in-class practices for high-quality RTL design (front-end and back-end) and Design Verification

 

 

ACADEMIC CREDENTIALS: 

MSEE + or PhD 

 

#LI-AP3

#LI-HYBRID

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