SerDes Analog Design Engineer

Mar 06, 2024
San Jose, United States
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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THE ROLE:

The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.

THE PERSON:

We’re looking for a system architect to join a fast-paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications.

KEY RESPONSIBILITIES:

The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:

  • Signal processing, data coding, and FEC algorithms
  • SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems
  • Behavioral modeling of different blocks in transceivers
  • Familiarity with optical link analysis and evaluation is a plus
  • Presenting design trade-off analyses and implementation recommendations with custom circuit designers
  • Signal modulation, coding, and FEC knowledge and experience
  • Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE, DFE, MLSD/MLSE) experience is preferred
  • Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.
  • ADC based SerDes architecture experience is a plus
  • Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus
  • Familiarity with Simulink/Matlab, C/C++ programming, Python
  • Experience with lab equipment for high-speed digital systems
  • Good background of statistics and signal processing
  • Good understanding of SI/PI basics for high-speed serial links
  • Excellent technical communication skills (presentations and documentation)
  • Team player

ACADEMIC CREDENTIALS:  

  • MSEE a must and Ph.D. preferred

LOCATION: 

  • Santa Jose, California

 

 

 

#LI-TB2

 




At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

The SerDes Architecture and Modeling Group has responsibilities in generating robust SerDes architecture and algorithms, creating silicon and system level specifications, developing and verifying SerDes design models, developing IBIS-AMI models for system level simulations and for customers, evaluating system performance margin trade-offs, analyzing system SI and PI, and bringing up and characterizing silicon.

THE PERSON:

We’re looking for a system architect to join a fast-paced transceiver design team. Our team stays ahead of the technology curve to deliver world-class programmable transceiver solutions for multiple FPGA platforms, supporting over 20 protocols with thousands of customer applications.

KEY RESPONSIBILITIES:

The successful candidate will be analytical, thorough, self-driven, and have an excellent track record in the following areas:

  • Signal processing, data coding, and FEC algorithms
  • SerDes architecture development including equalizers and time recovery for NRZ and PAM4 systems
  • Behavioral modeling of different blocks in transceivers
  • Familiarity with optical link analysis and evaluation is a plus
  • Presenting design trade-off analyses and implementation recommendations with custom circuit designers
  • Signal modulation, coding, and FEC knowledge and experience
  • Architecture experience with transceiver equalizers (TX FIR, RX analog FFE, CTLE, and DFE) – DSP (FFE, DFE, MLSD/MLSE) experience is preferred
  • Architecture experience with transceiver timing recovery, such as high speed PLLs, CDRs, etc.
  • ADC based SerDes architecture experience is a plus
  • Experience with using and developing transceiver modeling, analysis, and characterization tools – IBIS-AMI model development experience is a plus
  • Familiarity with Simulink/Matlab, C/C++ programming, Python
  • Experience with lab equipment for high-speed digital systems
  • Good background of statistics and signal processing
  • Good understanding of SI/PI basics for high-speed serial links
  • Excellent technical communication skills (presentations and documentation)
  • Team player

ACADEMIC CREDENTIALS:  

  • MSEE a must and Ph.D. preferred

LOCATION: 

  • Santa Jose, California

 

 

 

#LI-TB2

 

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