Server Power Integrity Engineer

May 12, 2024
Santa Clara, Cuba
... Not specified
... Intermediate
Full time
... Office work


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Server Power Integrity Engineer

 

Role:

AMD has an opening for Power Integrity engineer in Server Division working on platform power delivery network design and customer support for EPYC products.

 

The Person:

As a power integrity engineer on AMD server platform team, you will be directly working together with silicon architecture team and platform team to influence the design of server products. The main focus will be on system level PDN design and analysis, as well PDN performance optimization. You will have chance to show impact in both pre-silicon stage and post-silicon stage. For post-silicon stage, you will get chance to validate/test the noise in lab and perform correlation as well. more details is shown below:

  • Deep understanding of VRM working mechanism and both passive, active modeling
  • Board/system-level power delivery network AC+DC simulation for low-voltage/high-current supplies.
  • System-level signal integrity and power integrity understanding including silicon, package, and board.
  • Electromagnetic modeling of 3-D structures.
  • Experienced in power noise measurement, jitter measurement and analysis
  • A key responsibility of this position will be to work closely with the customer support organization and to support customers with power integrity issues.

 

Key Responsibilities:

An in-depth knowledge of the following is required:

  • Transmission line theory and microwave engineering concepts such as S-parameter, impedance, SSN, etc.
  • System-level timing analysis considering effects from silicon IO, package, and board.
  • State-of-the-art PCB stack up/construction.
  • In-depth knowledge of AC/DC power delivery, power integrity analysis.
  • Expertise in modeling with Sigrity PowerDC and PowerSI.

 

Academic Credentials:

  • BS-EE or MS-EE
  • 8+ years of proven experience in power integrity design and high-speed board-level design

 

Location:

Santa Clara, CA 

 

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Server Power Integrity Engineer

 

Role:

AMD has an opening for Power Integrity engineer in Server Division working on platform power delivery network design and customer support for EPYC products.

 

The Person:

As a power integrity engineer on AMD server platform team, you will be directly working together with silicon architecture team and platform team to influence the design of server products. The main focus will be on system level PDN design and analysis, as well PDN performance optimization. You will have chance to show impact in both pre-silicon stage and post-silicon stage. For post-silicon stage, you will get chance to validate/test the noise in lab and perform correlation as well. more details is shown below:

  • Deep understanding of VRM working mechanism and both passive, active modeling
  • Board/system-level power delivery network AC+DC simulation for low-voltage/high-current supplies.
  • System-level signal integrity and power integrity understanding including silicon, package, and board.
  • Electromagnetic modeling of 3-D structures.
  • Experienced in power noise measurement, jitter measurement and analysis
  • A key responsibility of this position will be to work closely with the customer support organization and to support customers with power integrity issues.

 

Key Responsibilities:

An in-depth knowledge of the following is required:

  • Transmission line theory and microwave engineering concepts such as S-parameter, impedance, SSN, etc.
  • System-level timing analysis considering effects from silicon IO, package, and board.
  • State-of-the-art PCB stack up/construction.
  • In-depth knowledge of AC/DC power delivery, power integrity analysis.
  • Expertise in modeling with Sigrity PowerDC and PowerSI.

 

Academic Credentials:

  • BS-EE or MS-EE
  • 8+ years of proven experience in power integrity design and high-speed board-level design

 

Location:

Santa Clara, CA 

 

#LI-LM1

#LI-HYBRID

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