WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

Responsibilities:

• Develop and execute pre-silicon verification test plans for DFT features of the next gen Zen architecture based Server SoC.
• Develop directed and random verification tests to fully validate the DFT functionality.
• Verify DFT design blocks and subsystems (such as JTAG, MBIST, high speed IO PHY, Scan, Security, Fuse, Clocks, Resets, etc) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
• Build test bench components including Agents, Monitors and Scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.
• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
• Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.

Required Qualifications:

• Good exposure to DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing)
• Strong background in Verilog, SystemVerilog (SV), SVA,  UVM verification methodologies and C++
• Strong debug skills and experience with debug tools such as Verdi.
• Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi
• Experience with scripting languages like Tcl/Perl/Ruby/Python
• Working knowledge of Unix/Linux OS, file version control.

Additional skills:

• Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus.
• Strong analytical/problem solving skills and pronounced attention to details
• Excellent written and verbal communication

 Educational Qualification

• Engineering Degree in Electronics/Electrical/Computer Science.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities:

• Develop and execute pre-silicon verification test plans for DFT features of the next gen Zen architecture based Server SoC.
• Develop directed and random verification tests to fully validate the DFT functionality.
• Verify DFT design blocks and subsystems (such as JTAG, MBIST, high speed IO PHY, Scan, Security, Fuse, Clocks, Resets, etc) using complex SV or C++ verification environments. Construct SystemVerilog and/or C/C++ models and test sequence libraries for simulation.
• Build test bench components including Agents, Monitors and Scoreboards for DUT. Compose tests, assertions, checkers, validation vectors and coverage bins to ensure verification completeness.
• Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
• Develop high coverage and cost effective test patterns, and take part in ATE bring-up.
• Post silicon ATE and System level debug support of the test patterns delivered. Optimize the test patterns to improve the test quality and reduce test costs.

Required Qualifications:

• Good exposure to DFT feature verification (such as JTAG, MBIST, SCAN, fuse, IO-PHY loopback testing)
• Strong background in Verilog, SystemVerilog (SV), SVA,  UVM verification methodologies and C++
• Strong debug skills and experience with debug tools such as Verdi.
• Experience with EDA simulation tools like Synopsys VCS, Cadence NCSIM, Verdi
• Experience with scripting languages like Tcl/Perl/Ruby/Python
• Working knowledge of Unix/Linux OS, file version control.

Additional skills:

• Experience in ATE debug, Synthesis, formal/LEC, or power analysis will be a plus.
• Strong analytical/problem solving skills and pronounced attention to details
• Excellent written and verbal communication

 Educational Qualification

• Engineering Degree in Electronics/Electrical/Computer Science.