WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SILICON DESIGN ENGINEER 2

THE ROLE:

As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. 

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

Job deliverables:

1. Setup ASIC QA flows for RTL design quality checks.
2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.
3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
5. Checking the flow errors, design errors & violations and reviewing the reports.
6. Debugging CDC, RDC issues and come up with the RTL fixes.
7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
9. Flows or Design porting to different technology libraries.
10. Generating RAMs based on targeted memory compilers and integrating with the RTL.
11. Running functional verification simulations as needed.

Job Requirements:

1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience
2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
3. Digital design and experience with RTL design in Verilog/SystemVerilog
4. Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation

5. Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces.

TCL, Perl, Python scripting

PREFERRED EXPERIENCE:

• Project level experience with design concepts and RTL implementation for same 
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics 
• Good understanding of computer organization/architecture 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 #LI-SR5 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER 2

THE ROLE:

As a Silicon Design Engineer, you will work with formal experts and designers to verify formal properties and drive convergence. 

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

Job deliverables:

1. Setup ASIC QA flows for RTL design quality checks.
2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains.
3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers.
5. Checking the flow errors, design errors & violations and reviewing the reports.
6. Debugging CDC, RDC issues and come up with the RTL fixes.
7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks.
8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc.
9. Flows or Design porting to different technology libraries.
10. Generating RAMs based on targeted memory compilers and integrating with the RTL.
11. Running functional verification simulations as needed.

Job Requirements:

1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 5+ years of relevant experience
2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes
3. Digital design and experience with RTL design in Verilog/SystemVerilog
4. Modern SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation

5. Preferred experience in AXI4 or NOC protocols or DRAM memory interfaces.

TCL, Perl, Python scripting

PREFERRED EXPERIENCE:

• Project level experience with design concepts and RTL implementation for same 
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics 
• Good understanding of computer organization/architecture 

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

 #LI-SR5