Silicon Design Engineer 2

Nov 30, 2023
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SILICON DESIGN ENGINEER 2   ::  SOC Verification 

 

Job Description:

The verification team is looking for a SOC Verification Engineer to contribute on the verification of  IPs and Subsystems. The individual will use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of IPs, subsystem and SOC designs. As a SOC Verificaton Engineer, you will work with verification experts and designers to verify the functionality and drive coverage closure. 

 

Responsibilities: 

  • Plan verification of complex digital design blocks by fully understanding the architecture and design specification.
  • Testbench development in System Verilog and UVM to complete verification of RTL design in an efficient manner.
  • Create and enhance constrained-random and/or directed verification scenarios.
  • Debug tests with design engineers to deliver functionally correct design block.
  • Responsible for verification quality metrics like pass rates, code coverage and functional coverage.

General requirements:         

  • Good exposure to UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
  • Understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Knowledge of standard protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
  • Knowledge of verification flows such as gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.

Special Requirements

  • Implementing verification environment using advanced verification methodology such as UVM or SystemVerilog.
  • Test plan development and test writing.
  • Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip.
  • Functional coverage writing, coverage collection and analysis, coverage closure.
  • Writing System Verilog assertions and assertion based verification; and.
  • Running regressions, automation using scripting languages such as PERL and verification closure.

 

Education Requirements:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER 2   ::  SOC Verification 

 

Job Description:

The verification team is looking for a SOC Verification Engineer to contribute on the verification of  IPs and Subsystems. The individual will use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of IPs, subsystem and SOC designs. As a SOC Verificaton Engineer, you will work with verification experts and designers to verify the functionality and drive coverage closure. 

 

Responsibilities: 

  • Plan verification of complex digital design blocks by fully understanding the architecture and design specification.
  • Testbench development in System Verilog and UVM to complete verification of RTL design in an efficient manner.
  • Create and enhance constrained-random and/or directed verification scenarios.
  • Debug tests with design engineers to deliver functionally correct design block.
  • Responsible for verification quality metrics like pass rates, code coverage and functional coverage.

General requirements:         

  • Good exposure to UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
  • Understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
  • Strong understanding of different phases of ASIC and/or full custom chip development is required.
  • Knowledge of standard protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus
  • Knowledge of verification flows such as gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
  • Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.

Special Requirements

  • Implementing verification environment using advanced verification methodology such as UVM or SystemVerilog.
  • Test plan development and test writing.
  • Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip.
  • Functional coverage writing, coverage collection and analysis, coverage closure.
  • Writing System Verilog assertions and assertion based verification; and.
  • Running regressions, automation using scripting languages such as PERL and verification closure.

 

Education Requirements:

  • Bachelors or Masters degree in computer engineering/Electrical Engineering 

 

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