Silicon Design Engineer 2

Feb 28, 2024
Hyderabad, India
... Not specified
... Intermediate
Full time
... Office work


WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SILICON DESIGN ENGINEER 2

 

THE ROLE:

The Core design team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients/server) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.

 

KEY RESPONSIBILITIES:

  • RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  • Design of x86 Core microarchitecture features, power management features, cache, coherency.
  • Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  • Responsible for the inter IP integration issues resolution
  • Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
  • Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
  • Micro-architecting and documentation of the design features

 

PREFERRED EXPERIENCE:

  • 0 to 3 years of experience in Digital IP/ASIC design and Verilog RTL development
  • Exposure to full IP design cycle, requirements definition, architecture and microarchitecture specification.
  • Should have the knowledge with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
  • Experience on Verilog RTL design and multiscale digital IP/ASIC projects.
  • Should possess expertise in front-end EDA tools.
  • Ability to program with scripting languages such as Python or Perl is a plus;
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
  • Excellent writing skills in the English language, editing and organizational skills required;
  • Good knowledge of engineering terminology used within the semiconductor industry;
  • Strong in digital design concepts;

 

 

ACADEMIC CREDENTIALS:

  • Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

 

LOCATION:

Hyderabad

 




Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER 2

 

THE ROLE:

The Core design team is responsible for development of ‘High performance and Ultralow power x86 microprocessor core’. The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops/ultra-books/think-clients/server) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes.

 

KEY RESPONSIBILITIES:

  • RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  • Design of x86 Core microarchitecture features, power management features, cache, coherency.
  • Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  • Responsible for the inter IP integration issues resolution
  • Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem.
  • Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
  • Micro-architecting and documentation of the design features

 

PREFERRED EXPERIENCE:

  • 0 to 3 years of experience in Digital IP/ASIC design and Verilog RTL development
  • Exposure to full IP design cycle, requirements definition, architecture and microarchitecture specification.
  • Should have the knowledge with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation.
  • Experience on Verilog RTL design and multiscale digital IP/ASIC projects.
  • Should possess expertise in front-end EDA tools.
  • Ability to program with scripting languages such as Python or Perl is a plus;
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements;
  • Excellent writing skills in the English language, editing and organizational skills required;
  • Good knowledge of engineering terminology used within the semiconductor industry;
  • Strong in digital design concepts;

 

 

ACADEMIC CREDENTIALS:

  • Master’s degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or Computer Science with a focus on computer architecture

 

LOCATION:

Hyderabad

 

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