Silicon Design Engineer 2
What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The DXIO FEINT/Implementation team is responsible for Synthesis, place & Route, Timing closure/CDC/LINT/DFx for very high speed (>2G) design with complex I/O clocking.
As a Design Engineer, you will be working with a diverse team of physical design engineers, RTL design engineers, and managers from NBIO IP team. You will drive physical implementation of IP through the entire physical design flow to achieve best PPA, while shortening the overall development schedule. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!
We are currently looking for a Design Engineer will focus on all physical implementation aspects of next generation IPs. This team deals with multiple I/O protocols including PCIe, SATA, Ethernet & Infinity Fabric link-layer. This team is a group of highly experienced ASIC design engineers working on High speed (>2G) designs with very complex clocking infrastructures. The team owns implementation activities including Synthesis & DFT, floorplan, placement, clock tree synthesis, routing, STA closure.
The team will work on cutting edge IP for these I/O protocols to achieve physical implementation with best PPA, including developing reference floorplans, implementation scripts for SoCs worldwide, and support SoCs worldwide.
<=1 years or more industry experience in Synthesis, Floor-planning, Placement, clock trees synthesis, Post Route Timing closure for high-speed >=2GHz designs.
CDC, PTPX, STA, LINT & DFT, IP, Physical design flow & scripting in TCL, Python
Location: Markham, Ontario.
Academic Credentials: Minimum B.S. or B.E.
Requisition Number: 169222
Country: Canada Province: Ontario City: Markham
AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.