WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

SILICON DESIGN ENGINEER 2

THE ROLE:

The RTG SOC team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

THE PERSON:

• Passionate about modern, complex processor architecture, digital design, and verification in general.
• Detail-oriented with strong analytical and debugging skills
• Must have good communication & analytical thinking skills
• Strong analytical and problem-solving skills and willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:

• Focus on timing, LINT and Clock domain crossing (CDC) closure to ensure high quality RTL.
• Engage with IPs/Designer to review CDC/LINT violations. 
• Prepare weekly summary reports and keep track of progress towards review closure. 
• Work closely with the RTL design, verification, and physical design teams to identify areas for automation and create solutions to improve productivity and quality.
• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
• Drive design and methodology improvements across teams to improve overall program execution
• Participate in defining and implementing Design for Power (DFP) methodologies (power-gating/voltage islands).

PREFERRED EXPERIENCE:

• Project level experience with design concepts and RTL implementation. Proficiency with Verilog RTL design language
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
• Proficiency with scripting languages such as Perl for developing in-house scripts/parses/automation is a big plus!
• Have a good understanding of entire design process from design specification, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, to Timing closure and Tape-out

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER 2

THE ROLE:

The RTG SOC team develops leading edge discrete graphics SOCs. The team owns SOC execution and is actively engaged from architecture to production. Working as part of the SOC leadership team, candidates will gain knowledge in system and IP level design, SOC architecture and implementation strategies.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

THE PERSON:

• Passionate about modern, complex processor architecture, digital design, and verification in general.
• Detail-oriented with strong analytical and debugging skills
• Must have good communication & analytical thinking skills
• Strong analytical and problem-solving skills and willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES:

• Focus on timing, LINT and Clock domain crossing (CDC) closure to ensure high quality RTL.
• Engage with IPs/Designer to review CDC/LINT violations. 
• Prepare weekly summary reports and keep track of progress towards review closure. 
• Work closely with the RTL design, verification, and physical design teams to identify areas for automation and create solutions to improve productivity and quality.
• Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation.
• Drive design and methodology improvements across teams to improve overall program execution
• Participate in defining and implementing Design for Power (DFP) methodologies (power-gating/voltage islands).

PREFERRED EXPERIENCE:

• Project level experience with design concepts and RTL implementation. Proficiency with Verilog RTL design language
• Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
• Proficiency with scripting languages such as Perl for developing in-house scripts/parses/automation is a big plus!
• Have a good understanding of entire design process from design specification, micro-architecture, RTL design and functional verification, Synthesis, Physical Design, to Timing closure and Tape-out

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering