WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

 
THE ROLE: 

The North America SoC Physical Design Team within the GPU Technologies and Engineering is looking for an experienced Design professional with strong industry experience to join the Full-Chip Timing Team.   As a member of the GPU Technologies and Engineering (G&E) group, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the architecture, IP design, front-end design/integration teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills, and be comfortable with large high-speed designs.

KEY RESPONSIBLITIES:

• Bring deep knowledge and experience in Physical design and full chip timing and STA sign-off and apply them to large, challenging, leading-edge designs to ensure high quality on time delivery.
• Collaborate with senior Full Chip Timing team members.
• Bring significant experience in effective team leadership to help mentor, coach and grow the RTG  Physical Design Team with an emphasis on positive influence on team morale and culture.
• Support the FCT flows for efficient full-chip timing analysis and closure.
• Experience and understanding of flow development and scripting.
• Strong Technical problem and debugging solving.
• Drive STA closure on critical and high performance clocks.

PREFERRED EXPERIENCE:

• Expert in STA and timing closure on complex SOC's in advanced process node.
• Extensive experience in ASIC Physical Design in latest process nodes.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics required.
• Must be a self-starter and able to independently and efficiently drive challenging and time critical tasks to on-time completion.
• Understanding of Place & route, Timing Analysis, clock tree distribution, Physical Verification, Chip Integration.
• Flow development and support experience.
• Experience with tcl/Perl/Shell scripting.
• Experience on 3D stack timing analysis and sign-off a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

#LI-DNI

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

 
THE ROLE: 

The North America SoC Physical Design Team within the GPU Technologies and Engineering is looking for an experienced Design professional with strong industry experience to join the Full-Chip Timing Team.   As a member of the GPU Technologies and Engineering (G&E) group, you will help bring to life cutting-edge designs. As a member of the Physical Design team, you will work closely with the architecture, IP design, front-end design/integration teams, and product engineers to achieve first pass silicon success.

THE PERSON:

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills, and be comfortable with large high-speed designs.

KEY RESPONSIBLITIES:

• Bring deep knowledge and experience in Physical design and full chip timing and STA sign-off and apply them to large, challenging, leading-edge designs to ensure high quality on time delivery.
• Collaborate with senior Full Chip Timing team members.
• Bring significant experience in effective team leadership to help mentor, coach and grow the RTG  Physical Design Team with an emphasis on positive influence on team morale and culture.
• Support the FCT flows for efficient full-chip timing analysis and closure.
• Experience and understanding of flow development and scripting.
• Strong Technical problem and debugging solving.
• Drive STA closure on critical and high performance clocks.

PREFERRED EXPERIENCE:

• Expert in STA and timing closure on complex SOC's in advanced process node.
• Extensive experience in ASIC Physical Design in latest process nodes.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics required.
• Must be a self-starter and able to independently and efficiently drive challenging and time critical tasks to on-time completion.
• Understanding of Place & route, Timing Analysis, clock tree distribution, Physical Verification, Chip Integration.
• Flow development and support experience.
• Experience with tcl/Perl/Shell scripting.
• Experience on 3D stack timing analysis and sign-off a plus.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering.

#LI-DNI