WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

SILICON DESIGN ENGINEER

The Role:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for leading edge AMD products. It is also responsible for DFX design methodology and automation tools development to support the global DFX engineering teams across AMD.

The Person:

As a Silicon Design Engineer, you will be working with a diverse team of design engineers and managers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

The following highlights a successful candidate:

• Demonstrated DFT design skills and project execution experience
• Excellent verbal and written communication and interpersonal skills
• Self-starter, driven and disciplined with a dedication to meeting deadlines
• Has an aptitude to thrive in a fast-paced multi-tasking environment
• Comfortable working independently, and yet can work collaboratively with various levels and organization functions.

Key Responsibilities:

• Working with a multi-discipline and international team of engineers on design-for-test (DFT) architecture, design, tools and methodology initiatives
• Performing scan insertion, ATPG verification and test pattern generation
• Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
• Writing and maintaining DFT documentation and specifications
• Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis

Preferred Experience:

• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
• Knowledge in scan compression architecture, scan insertion and ATPG methodologies
• Knowledge in EDA tools/methodology, such as logic synthesis, DFT scan and ATPG, design check, equivalency checking, static timing analysis
• Experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, shell, Perl, Python, etc.), C++ programming

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER

The Role:

Central DFX (CDFX) is a centralized ASIC design group within AMD’s Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for leading edge AMD products. It is also responsible for DFX design methodology and automation tools development to support the global DFX engineering teams across AMD.

The Person:

As a Silicon Design Engineer, you will be working with a diverse team of design engineers and managers from various global design locations on design-for-test (DFT) design and implementation, tool and methodology development, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

The following highlights a successful candidate:

• Demonstrated DFT design skills and project execution experience
• Excellent verbal and written communication and interpersonal skills
• Self-starter, driven and disciplined with a dedication to meeting deadlines
• Has an aptitude to thrive in a fast-paced multi-tasking environment
• Comfortable working independently, and yet can work collaboratively with various levels and organization functions.

Key Responsibilities:

• Working with a multi-discipline and international team of engineers on design-for-test (DFT) architecture, design, tools and methodology initiatives
• Performing scan insertion, ATPG verification and test pattern generation
• Developing CAD software, scripts and other support technology to enable successful construction of DFT logics in complex SoC design
• Writing and maintaining DFT documentation and specifications
• Providing DFT feature bring-up and pattern debug support to production engineering team during first silicon bring-up, qualification and failure analysis

Preferred Experience:

• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design
• Knowledge in scan compression architecture, scan insertion and ATPG methodologies
• Knowledge in EDA tools/methodology, such as logic synthesis, DFT scan and ATPG, design check, equivalency checking, static timing analysis
• Experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
• Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, shell, Perl, Python, etc.), C++ programming

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering