WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. This is who we are at our best. One Company. One Team. 

AMD together we advance_

THE ROLE:

AMD's Adaptive-Embedded Computing group is seeking an experienced IC design engineer for the Design & Development of high-performance FPGA IP blocks in the company’s next generation products. Successful candidates will be responsible for design and development of assigned IP blocks to ensure RTL meets all defined quality metrics.  You will also provide back-end design closure support for STA, EM, IR and power analysis. The other responsibilities will include implementation of system level design in FPGA using different FPGA IP blocks which meets the front-end design criteria and use the design to test the silicon on Bench or ATE tester. As a member of the Silicon Design group, you will have wide array of opportunities to work closely with functional architecture, Programable fabric, integration and SW teams to craft and implement new Programable Logic solutions, including new architectures, IP design and development of new tools, flows & Methodology.

THE PERSON:

The type of person who will be successful in this role is highly inquisitive and a team player who communicates proactively. They will exhibit excellent written and verbal communication skills and will be highly analytical. The candidate should enjoy collaborating with engineers with diverse skillsets and bringing their expertise to bear on solving challenging Programable logic problems. The succesful candidate will have comprehensive knowledge of ASIC design methodology. 

KEY RESPONSIBILITIES:

• Implement FPGA IP in physical design flow using ICC2, STA.
• Run static checks using LINT, LEC, CDC
• Support RTL functional simulation and verification
• Provide physical implementation design support using STA, EM, IR, Power analysis tools.
• Develop SDC constraint and do timing analysis using Prime Time or equivalent timing analysis tool.
• Implement IP in FPGA environment using Vivado or similar tools/flows.
• Improve the efficiency and quality using scripting and programming.
• Support Silicon testing on bench or ATE tester.

PREFERRED EXPERIENCE:

• Comprehensive knowledge of ASIC design methodology.

• Prior work experience in FPGA design using VIVADO tool and silicon testing is a plus.

• VLSI Fundamentals, Digital Systems & Circuits design, deep submicron CMOS design based on FinFETs technology
• Physical Design Tools: RTL to GDSII, ICC2, PnR, CTS, Star RC, STA.
• Circuit Design Tools: Cadence (Virtuoso - Schematics and Layout), ADE-XL, Spectre.
• Verilog, Perl/Python/C++ scripting and programming.
• HSPICE, Wave Viewer, ModelSim. 

ACADEMIC CREDENTIALS:

• BS/MS (Computer Science, Computer Engineering, Electrical Engineering, or related equivalent)

 LOCATION: 

• San Jose, CA

#LI-EV1

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

AMD's Adaptive-Embedded Computing group is seeking an experienced IC design engineer for the Design & Development of high-performance FPGA IP blocks in the company’s next generation products. Successful candidates will be responsible for design and development of assigned IP blocks to ensure RTL meets all defined quality metrics.  You will also provide back-end design closure support for STA, EM, IR and power analysis. The other responsibilities will include implementation of system level design in FPGA using different FPGA IP blocks which meets the front-end design criteria and use the design to test the silicon on Bench or ATE tester. As a member of the Silicon Design group, you will have wide array of opportunities to work closely with functional architecture, Programable fabric, integration and SW teams to craft and implement new Programable Logic solutions, including new architectures, IP design and development of new tools, flows & Methodology.

THE PERSON:

The type of person who will be successful in this role is highly inquisitive and a team player who communicates proactively. They will exhibit excellent written and verbal communication skills and will be highly analytical. The candidate should enjoy collaborating with engineers with diverse skillsets and bringing their expertise to bear on solving challenging Programable logic problems. The succesful candidate will have comprehensive knowledge of ASIC design methodology. 

KEY RESPONSIBILITIES:

• Implement FPGA IP in physical design flow using ICC2, STA.
• Run static checks using LINT, LEC, CDC
• Support RTL functional simulation and verification
• Provide physical implementation design support using STA, EM, IR, Power analysis tools.
• Develop SDC constraint and do timing analysis using Prime Time or equivalent timing analysis tool.
• Implement IP in FPGA environment using Vivado or similar tools/flows.
• Improve the efficiency and quality using scripting and programming.
• Support Silicon testing on bench or ATE tester.

PREFERRED EXPERIENCE:

• Comprehensive knowledge of ASIC design methodology.

• Prior work experience in FPGA design using VIVADO tool and silicon testing is a plus.

• VLSI Fundamentals, Digital Systems & Circuits design, deep submicron CMOS design based on FinFETs technology
• Physical Design Tools: RTL to GDSII, ICC2, PnR, CTS, Star RC, STA.
• Circuit Design Tools: Cadence (Virtuoso - Schematics and Layout), ADE-XL, Spectre.
• Verilog, Perl/Python/C++ scripting and programming.
• HSPICE, Wave Viewer, ModelSim. 

ACADEMIC CREDENTIALS:

• BS/MS (Computer Science, Computer Engineering, Electrical Engineering, or related equivalent)

 LOCATION: 

• San Jose, CA

#LI-EV1