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SILICON DESIGN ENGINEER - Timing Methodology

THE ROLE:

AMD AEComputing Methodology team is seeking an engineer with background and / or interest in STA  analysis to help investigate, develop, and deploy new techniques to optimize and analyze macro, block and/or SOC timing. Since this is a Design (not CAD) methodology role, the candidate should be comfortable with Place and route and custom circuit design/ analysis and associated methodologies, tools and flow thereof.

As a member of our team, you’d help investigate, develop, and deploy new techniques to optimize and analyze SOCs and 3DICs across various aspects of block, SOC and 3DIC designs, including, but not limited to Timing closure, constraints and Physical design. This would help us create the next generation of Adaptive and Embedded silicon products including FPGA, APUs, DPUs, AIE and IO subsystems, Monolithic and 3D SOCs to give unparalleled flexibility to AMD customers

THE PERSON:

You are self-motivated energetic engineer who works to optimize/improve the workflow, anticipates technical issues, has deep analytical and problem-solving skills, and enjoys a competitive pace. In addition, you have strong written and verbal skills, excellent presentation skills, strong sense of teamwork, have an exceptional attention to detail and are willing to learn and ready to take on problems. . 

KEY RESPONSIBILITIES:

• • Methodology development and new methodology evaluations for Block level and Chip Level timing including, but not limited to constraints, budgeting, timing closure, data handoffs, variation robustness, margins, multi-scenario and timing-exceptions.
  • Evaluate next generation methodologies related to STA, 3DIC - SSIT, AoA, CoWoS, etc.
  • Interface with various engineering groups, including Block design, CAD, software, and product engineering to guide design and analysis styles and review verification of blocks
  • Develop/ enhance methodologies Timing model generation and verification
  • Debug design and flow issues related to Extraction, Noise, timing closure/ modeling/ constraint propgations, etc.
  • Evaluate and establish timing closure requirements for advanced SOC/ 3D-SOC designs and architectures.
  •  

   

PREFERRED EXPERIENCE:

• • High Speed logic design and synthesis,
  • Tool driven place and route
  • Timing Analysis and Optimization
  • Electromigration and IR Drop analysis
  • Low Power design Techniques
  • Experience with Physical design and analysis tools such as ICC2, Primetime, Nanotime, Fishtail.
  • Experience with one or more of the following tool scripting Perl, Python and TCL are preferred.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering 

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SILICON DESIGN ENGINEER - Timing Methodology

THE ROLE:

AMD AEComputing Methodology team is seeking an engineer with background and / or interest in STA  analysis to help investigate, develop, and deploy new techniques to optimize and analyze macro, block and/or SOC timing. Since this is a Design (not CAD) methodology role, the candidate should be comfortable with Place and route and custom circuit design/ analysis and associated methodologies, tools and flow thereof.

As a member of our team, you’d help investigate, develop, and deploy new techniques to optimize and analyze SOCs and 3DICs across various aspects of block, SOC and 3DIC designs, including, but not limited to Timing closure, constraints and Physical design. This would help us create the next generation of Adaptive and Embedded silicon products including FPGA, APUs, DPUs, AIE and IO subsystems, Monolithic and 3D SOCs to give unparalleled flexibility to AMD customers

THE PERSON:

You are self-motivated energetic engineer who works to optimize/improve the workflow, anticipates technical issues, has deep analytical and problem-solving skills, and enjoys a competitive pace. In addition, you have strong written and verbal skills, excellent presentation skills, strong sense of teamwork, have an exceptional attention to detail and are willing to learn and ready to take on problems. . 

KEY RESPONSIBILITIES:

• • Methodology development and new methodology evaluations for Block level and Chip Level timing including, but not limited to constraints, budgeting, timing closure, data handoffs, variation robustness, margins, multi-scenario and timing-exceptions.
  • Evaluate next generation methodologies related to STA, 3DIC - SSIT, AoA, CoWoS, etc.
  • Interface with various engineering groups, including Block design, CAD, software, and product engineering to guide design and analysis styles and review verification of blocks
  • Develop/ enhance methodologies Timing model generation and verification
  • Debug design and flow issues related to Extraction, Noise, timing closure/ modeling/ constraint propgations, etc.
  • Evaluate and establish timing closure requirements for advanced SOC/ 3D-SOC designs and architectures.
  •  

   

PREFERRED EXPERIENCE:

• • High Speed logic design and synthesis,
  • Tool driven place and route
  • Timing Analysis and Optimization
  • Electromigration and IR Drop analysis
  • Low Power design Techniques
  • Experience with Physical design and analysis tools such as ICC2, Primetime, Nanotime, Fishtail.
  • Experience with one or more of the following tool scripting Perl, Python and TCL are preferred.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering