SMTS Package Design Engineer

May 16, 2024
Markham, Canada
... Not specified
... Intermediate
Full time
... Office work

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

SMTS PACKAGING ENGINEER 

 

Key Responsibilities:

  • Codesign with SOC design teams to optimize the silicon floorplan and to create a custom ubump/C4 bump matrix
  • Design silicon or organic interposers for advanced chiplet packaging solutions
  • Codesign substrate layouts with SI, PI, and Platform teams to meet cost/performance targets.
  • Scope out the feasibility of various architectural power/performance/cost design scenarios and determine the packaging solution matrix for each
  • Contribute to the development and enhancements of process and methodologies to improve design efficiency.
  • Mentor Junior Colleagues to enhance layout design practices.

 

Education Requirements:

 

  • A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science

Skills and Experience Requirements:

  • Experience on Package Design and/or ASIC Chip Design
  • Experienced user of Package/PCB design tools(APD) and/or Silicon Place and Route tools(3DIC, ICC2)
  • Experience with physical verification(DRC/LVS, Calibre)
  • Experience with programming(TCL, Perl, Python)
  • Excellent communication and organizational skills

Team player who can work independently with minimal supervision

 

Location:  Markham, Canada

 

#LI-DA1

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

 

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS PACKAGING ENGINEER 

 

Key Responsibilities:

  • Codesign with SOC design teams to optimize the silicon floorplan and to create a custom ubump/C4 bump matrix
  • Design silicon or organic interposers for advanced chiplet packaging solutions
  • Codesign substrate layouts with SI, PI, and Platform teams to meet cost/performance targets.
  • Scope out the feasibility of various architectural power/performance/cost design scenarios and determine the packaging solution matrix for each
  • Contribute to the development and enhancements of process and methodologies to improve design efficiency.
  • Mentor Junior Colleagues to enhance layout design practices.

 

Education Requirements:

 

  • A. Sc. in Electrical Engineering, Computer Engineering, or Engineering Science

Skills and Experience Requirements:

  • Experience on Package Design and/or ASIC Chip Design
  • Experienced user of Package/PCB design tools(APD) and/or Silicon Place and Route tools(3DIC, ICC2)
  • Experience with physical verification(DRC/LVS, Calibre)
  • Experience with programming(TCL, Perl, Python)
  • Excellent communication and organizational skills

Team player who can work independently with minimal supervision

 

Location:  Markham, Canada

 

#LI-DA1

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