WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

THE ROLE:

This role bridges the gap between design and test groups. The candidate will be involved with the design teams early in the product life cycle getting to know the architecture & pattern generation/delivery flows and support the test engineering group with post-Si pattern bring-up.     

Key Responsibilities:

• Develop processes and methodologies for improving test time, yield, pattern quality, and product quality being delivered to our customers.   
• Help test engineering team bring-up ATE patterns as quickly as possible.
• Track all silicon bring-up issues, define, and drive the corrective actions for future projects.
• Work with DFT architect to understand the architecture and help verify DFT features in RTL
• Develop and debug scan test setup in RTL
• Translate IP level scan patterns to SoC level and verify the patterns in gate level VCS simulation.

PREFERRED EXPERIENCE:

• Demonstrated DFT experience and should have been involved in DFT efforts for large processor and/or SoC Designs.
• Knowledge about industrial standards and practices in DFT, including SCAN/ATPG, JTAG & MBIST.
• Knowledge of Verilog and experience with simulator & waveform debugging tools.
• Exposure to post-silicon testing and tester pattern debug required.
• Ability to solve test time & test quality issues for DFT content

ACADEMIC CREDENTIALS: 

• Bachelor’s or Master’s in computer engineering or computer science or electrical engineering, or comparable disciplines

LOCATION:

Austin, TX

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At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

At AMD, your base pay is one part of your total rewards package.  Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

THE ROLE:

This role bridges the gap between design and test groups. The candidate will be involved with the design teams early in the product life cycle getting to know the architecture & pattern generation/delivery flows and support the test engineering group with post-Si pattern bring-up.     

Key Responsibilities:

• Develop processes and methodologies for improving test time, yield, pattern quality, and product quality being delivered to our customers.   
• Help test engineering team bring-up ATE patterns as quickly as possible.
• Track all silicon bring-up issues, define, and drive the corrective actions for future projects.
• Work with DFT architect to understand the architecture and help verify DFT features in RTL
• Develop and debug scan test setup in RTL
• Translate IP level scan patterns to SoC level and verify the patterns in gate level VCS simulation.

PREFERRED EXPERIENCE:

• Demonstrated DFT experience and should have been involved in DFT efforts for large processor and/or SoC Designs.
• Knowledge about industrial standards and practices in DFT, including SCAN/ATPG, JTAG & MBIST.
• Knowledge of Verilog and experience with simulator & waveform debugging tools.
• Exposure to post-silicon testing and tester pattern debug required.
• Ability to solve test time & test quality issues for DFT content

ACADEMIC CREDENTIALS: 

• Bachelor’s or Master’s in computer engineering or computer science or electrical engineering, or comparable disciplines

LOCATION:

Austin, TX

#LI-TW2

#HYBRID