SMTS Silicon Design Engineer - 161602

May 12, 2022
Santa Clara, United States
... Not specified
... Senior
Full time
... Office work

What you do at AMD changes everything 

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


ASIC Physical Design Technical Lead - SMTS



1. Technical lead of five to eight senior level engineers
2. Tasks to include  Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis,Full Chip Timing, Constraints, Top-level clock planning, Physical Verification and Sign Off
3. Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
4. Drive and hands-on flow development and scripting
5. Technical and schedule discussion with multi-site engineers and managers 


1. 10+ years experience with BSEE/BSCS or 8+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII
2. Excellent analytical and problem solving skills along with attention to details
3. Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations.

4. Experience in Full Chip pipelining and buffering, HFN buffering and feed through planning will be plus.

5. Experince in Full Chip Timing closure.

6.  Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding.
7. Hands on experience in taping out  7nm, 10nm, and 28nm SOC
8. Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
9. Strong communication, Time Management, and Presentation Skills
10. Must be a self-starter, and be able to independently and efficiently drive tasks to completion
11. Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player



Requisition Number: 161602 
Country: United States State: California City: Santa Clara 
Job Function: Design

Benefits offered are described here.

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