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We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

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SMTS SILICON DESIGN ENGINEER

Lead ASIC Security Design Verification Engineer

Position Overview

We are seeking a Lead ASIC Security Design Verification Engineer to drive verification strategy and lead a team of engineers. The role involves architecting verification environments, mentoring team members, and ensuring robust security implementations in complex ASIC designs.

Essential Responsibilities

• Lead and manage a team of design verification engineers
• Define and drive verification methodology and strategy for security-focused ASIC projects
• Architect advanced verification environments using UVM methodology
• Review and approve verification plans, test scenarios, and coverage metrics
• Guide technical decisions for verification infrastructure and framework development
• Establish best practices for security verification across projects
• Drive cross-functional collaboration with design, software, and product teams
• Provide technical leadership in verification reviews and project meetings
• Mentor and develop team members' technical and professional growth

Required Qualifications

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field
• 10+ years of Hardware Engineering experience with at least 5 years in lead verification roles
• Proven track record of leading complex verification projects and teams
• Expert-level knowledge in RTL design verification using Verilog/System Verilog/UVM methodology
• In-depth understanding of security protocols and cryptographic implementations:
• Symmetric and asymmetric cryptography
• Public/private key infrastructure
• Hash functions and random number generators
• Encryption/signature algorithms (AES, SHA, GMAC)
• Inline cryptography
• Advanced programming skills in Verilog, C/C++, Python, and Perl
• Strong experience in verification planning and coverage-driven verification
• Exceptional problem-solving and debugging skills
• Outstanding leadership and communication abilities

Preferred Qualifications

• Master's degree in Electrical Engineering
• Experience leading security-critical tape-outs
• Expertise in hardware security architecture and threat modeling
• Knowledge of formal verification methodologies
• Experience with verification IP development and reuse strategies
• Track record of implementing verification process improvements
• Publications or patents in hardware security or verification

Leadership Competencies

• Proven ability to build and lead high-performing technical teams
• Excellence in project planning and execution
• Strong decision-making and problem-solving abilities
• Effective stakeholder management skills
• Ability to mentor and develop team members
• Strategic thinking and innovation mindset

Technical Leadership

• Establish verification standards and methodologies
• Drive adoption of new verification technologies and tools
• Lead technical reviews and design discussions
• Guide architectural decisions for verification environments
• Contribute to organizational verification strategy

 #LI-SR4

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

SMTS SILICON DESIGN ENGINEER

Lead ASIC Security Design Verification Engineer

Position Overview

We are seeking a Lead ASIC Security Design Verification Engineer to drive verification strategy and lead a team of engineers. The role involves architecting verification environments, mentoring team members, and ensuring robust security implementations in complex ASIC designs.

Essential Responsibilities

• Lead and manage a team of design verification engineers
• Define and drive verification methodology and strategy for security-focused ASIC projects
• Architect advanced verification environments using UVM methodology
• Review and approve verification plans, test scenarios, and coverage metrics
• Guide technical decisions for verification infrastructure and framework development
• Establish best practices for security verification across projects
• Drive cross-functional collaboration with design, software, and product teams
• Provide technical leadership in verification reviews and project meetings
• Mentor and develop team members' technical and professional growth

Required Qualifications

• Bachelor's degree in Engineering, Information Systems, Computer Science, or related field
• 10+ years of Hardware Engineering experience with at least 5 years in lead verification roles
• Proven track record of leading complex verification projects and teams
• Expert-level knowledge in RTL design verification using Verilog/System Verilog/UVM methodology
• In-depth understanding of security protocols and cryptographic implementations:
• Symmetric and asymmetric cryptography
• Public/private key infrastructure
• Hash functions and random number generators
• Encryption/signature algorithms (AES, SHA, GMAC)
• Inline cryptography
• Advanced programming skills in Verilog, C/C++, Python, and Perl
• Strong experience in verification planning and coverage-driven verification
• Exceptional problem-solving and debugging skills
• Outstanding leadership and communication abilities

Preferred Qualifications

• Master's degree in Electrical Engineering
• Experience leading security-critical tape-outs
• Expertise in hardware security architecture and threat modeling
• Knowledge of formal verification methodologies
• Experience with verification IP development and reuse strategies
• Track record of implementing verification process improvements
• Publications or patents in hardware security or verification

Leadership Competencies

• Proven ability to build and lead high-performing technical teams
• Excellence in project planning and execution
• Strong decision-making and problem-solving abilities
• Effective stakeholder management skills
• Ability to mentor and develop team members
• Strategic thinking and innovation mindset

Technical Leadership

• Establish verification standards and methodologies
• Drive adoption of new verification technologies and tools
• Lead technical reviews and design discussions
• Guide architectural decisions for verification environments
• Contribute to organizational verification strategy

 #LI-SR4